add SDRAM clock output

diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py
index 58e7c027f2ab3157092f6afcf8c4b45113f2353f..ce6ba4364e43fd3492b531e64389c13434afa2fa 100644 (file)
--- a/src/bsv/peripheral_gen/sdram.py
+++ b/src/bsv/peripheral_gen/sdram.py
@@ -35,6 +35,7 @@ class sdram(PBase):
         return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
                 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
                 'sdrcke': 'ifc_sdram_out.osdr_cke',
+                'sdrclk': 'ifc_sdram_out.osdr_clock',
                 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
                 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
                 }.get(pname, '')

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 80a51296d6b9e18d8490b4330532c50882921dec..00d97e49f41e0de1bddeb57f8131c6ac3061ed49 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -175,7 +175,7 @@ def sdram1(suffix, bank):
         buspins.append("SDRAD%d+" % i)
     for i in range(2):
         buspins.append("SDRBA%d+" % i)
-    buspins += ['SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
+    buspins += ['SDRCLK+', 'SDRCKE+', 'SDRRASn+', 'SDRCASn+', 'SDRWEn+',
                 'SDRCSn0+']
     return (buspins, inout)