m = Module()
m.submodules.l = l = SRLatch(sync=False) # async latch
- # record current version of q in a sync'd register
- cq = Signal() # resets to 0
- m.d.sync += cq.eq(l.q)
-
# reset on go HI, set on dest and issue
m.d.comb += l.s.eq(self.issue_i & self.reg_i)
m.d.comb += l.r.eq(self.go_i)
m.d.comb += self.fwd_o.eq((l.q) & self.hazard_i) # & ~self.issue_i)
# Register Select. Activated on go read/write and *current* latch set
- m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
-
- m.d.comb += self.q_o.eq(cq | l.q)
+ m.d.comb += self.q_o.eq(l.qlq)
+ m.d.comb += self.rsel_o.eq(self.q_o & self.go_i)
return m
m = Module()
m.submodules.l = l = SRLatch(sync=False) # async latch
- # record current version of q in a sync'd register
- cq = Signal() # resets to 0
- m.d.sync += cq.eq(l.q)
-
# reset on go HI, set on dest and issue
m.d.comb += l.s.eq(self.issue_i & self.pend_i)
m.d.comb += l.r.eq(self.go_i)
# wait out
- m.d.comb += self.wait_o.eq((cq | l.q) & ~self.issue_i)
+ m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
return m
from nmigen import Module, Signal, Cat, Array, Const, Elaboratable, Repl
from nmigen.lib.coding import Decoder
-from nmutil.latch import SRLatch, latchregister
-
from scoreboard.shadow_fn import ShadowFn
m = Module()
m.submodules.sl = sl = SRLatch(sync=False)
- cq = Signal() # resets to 0
- m.d.sync += cq.eq(sl.q)
-
m.d.comb += sl.s.eq(self.shadow_i & self.issue_i & ~self.s_good_i)
m.d.comb += sl.r.eq(self.s_good_i | (self.issue_i & ~self.shadow_i))
- m.d.comb += self.recover_o.eq((cq | sl.q) & self.s_fail_i)
- m.d.comb += self.shadow_o.eq((cq | sl.q))
+ m.d.comb += self.recover_o.eq(sl.qlq & self.s_fail_i)
+ m.d.comb += self.shadow_o.eq(sl.qlq)
return m