m = Module()
# XXX TODO, actual DIV code here. this class would be
- # "step one" which takes the pre-normalised data and
+ # "step one" which takes the pre-normalised data (see ispec) and
# *begins* the processing phase (enters the massive DIV
- # pipeline chain)
+ # pipeline chain) - see ospec.
# store intermediate tests (and zero-extended mantissas)
am0 = Signal(len(self.i.a.m)+1, reset_less=True)
-"""IEEE754 Floating Point Divider
+"""IEEE754 Floating Point Divider
Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
"""
self.o = self.ospec()
def ispec(self):
- return FPDivStage0Data(self.width, self.id_wid)
+ return FPDivStage0Data(self.width, self.id_wid) # Q/Rem (etc) in...
def ospec(self):
- return FPDivStage0Data(self.width, self.id_wid)
+ return FPDivStage0Data(self.width, self.id_wid) # ... Q/Rem (etc) out
def process(self, i):
return self.o
# XXX TODO, actual DIV code here. this class would be
# "step two" and is the main "chain". tons of these needed.
- # here is where Q and R are used, TODO: those are in FPDivStage0Data.
+ # here is where Q and R are used, TODO: those need to be in
+ # FPDivStage0Data.
# store intermediate tests (and zero-extended mantissas)
am0 = Signal(len(self.i.a.m)+1, reset_less=True)
self.o = self.ospec()
def ispec(self):
- return FPDivStage0Data(self.width, self.id_wid)
+ return FPDivStage0Data(self.width, self.id_wid) # Q/Rem in...
def ospec(self):
- return FPAddStage1Data(self.width, self.id_wid)
+ return FPAddStage1Data(self.width, self.id_wid) # out to post-process
def process(self, i):
return self.o