add rom debugger

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
index f89288c075212bcf5ca63e9d48afeebb71c3a220..5e78726955732ef9a977a5efae0ba428be3e9d94 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_rom.py
@@ -6,7 +6,7 @@ import unittest
 
 from soc.fu.test.common import (
     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
-    
+
 def b(x):
     return int.from_bytes(x.to_bytes(8, byteorder='little'),
                           byteorder='big', signed=False)
@@ -20,13 +20,13 @@ default_mem = { 0x10000:    # PARTITION_TABLE_2
 
                 0x40000:     # RADIX_SECOND_LEVEL
                         #         V = 1 L = 1 SW = 0 RPN = 0
-                           # R = 1 C = 1 ATT = 0 EAA 0x7
+                           # R = 1 C = 1 ATT = 0 EAA 0x7
                 b(0xc000000000000187),
 
                 0x1000000:   # PROCESS_TABLE_3
                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
                 b(0x40000000000300ad),
-            }    
+            }
 
 
 class MMUTestCase(TestAccumulatorBase):
@@ -44,12 +44,16 @@ class MMUTestCase(TestAccumulatorBase):
         initial_sprs = {}
         self.add_case(Program(lst, bigendian),
                       initial_regs, initial_sprs)
+class RomDBG():
+    def __init__(self):
+        self.rom = default_mem
+        self.debug = open("/tmp/rom.log","w")
 
-rom = None
+rom_dbg = RomDBG()
 
 if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
-    suite.addTest(TestRunner(MMUTestCase().test_data,default_mem))
+    suite.addTest(TestRunner(MMUTestCase().test_data,rom_dbg))
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/soc/simple/test/test_runner_mmu_rom.py b/src/soc/simple/test/test_runner_mmu_rom.py
index 8e9d9a44637647ca183b9f80a0f3f31821ed60d7..fe055ef91fc6cfa5fd428b51fbeeac9821ca2c01 100644 (file)
--- a/src/soc/simple/test/test_runner_mmu_rom.py
+++ b/src/soc/simple/test/test_runner_mmu_rom.py
@@ -31,7 +31,37 @@ from soc.fu.compunits.test.test_compunit import (setup_test_memory,
                                                  check_sim_memory)
 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
 from nmutil.util import wrap
-from soc.experiment.test.test_mmu_dcache import wb_get
+
+stop = False
+
+def wb_get(c, mem, name):
+    """simulator process for getting memory load requests
+    """
+    global stop
+    # mem = mem
+
+    while not stop:
+        while True: # wait for dc_valid
+            if stop:
+                return
+            cyc = yield (c.wb_out.cyc)
+            stb = yield (c.wb_out.stb)
+            if cyc and stb:
+                break
+            yield
+        addr = (yield c.wb_out.adr) << 3
+        if addr not in mem.rom:
+            mem.debug.write("%s LOOKUP FAIL %x\n" % (name, addr))
+            stop = True
+            return
+
+        yield
+        data = mem.rom[addr]
+        yield c.wb_in.dat.eq(data)
+        mem.debug.write("%s get %x data %x\n" % (name, addr, data))
+        yield c.wb_in.ack.eq(1)
+        yield
+        yield c.wb_in.ack.eq(0)
 
 
 def setup_i_memory(imem, startaddr, instructions):
@@ -166,6 +196,7 @@ class TestRunner(FHDLTestCase):
         sim.add_clock(1e-6)
 
         def process():
+            global stop
 
             # start in stopped
             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
@@ -311,6 +342,7 @@ class TestRunner(FHDLTestCase):
 
                     print("after test %s reg %2d value %x" %
                           (test.name, int_reg, value))
+        stop = True
 
         styles = {
             'dec': {'base': 'dec'},