code-comments for LDSTCompUnit

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 807d15bfb793fd5bcaf5a2bdefb0aca5a2f47537..62333caed6a35d572995c05ffaf97ddb4b368943 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -105,7 +105,7 @@ class LDSTCompUnitRecord(CompUnitRecord):
         self.ad = go_record(1, name="cu_ad")  # address go in, req out
         self.st = go_record(1, name="cu_st")  # store go in, req out
 
-        self.exception_o = LDSTException("exc")
+        self.exception_o = LDSTException("exc_o")
 
         self.ld_o = Signal(reset_less=True)  # operation is a LD
         self.st_o = Signal(reset_less=True)  # operation is a ST
@@ -533,11 +533,13 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         return m
 
     def get_out(self, i):
-        """make LDSTCompUnit look like RegSpecALUAPI"""
+        """make LDSTCompUnit look like RegSpecALUAPI.  these correspond
+        to LDSTOutputData o and o1 respectively.
+        """
         if i == 0:
-            return self.data_o
+            return self.data_o # LDSTOutputData.regspec o
         if i == 1:
-            return self.addr_o
+            return self.addr_o # LDSTOutputData.regspec o1
         # return self.dest[i]
 
     def get_fu_out(self, i):

diff --git a/src/soc/fu/ldst/pipe_data.py b/src/soc/fu/ldst/pipe_data.py
index 0c374d095de73810c284d9d72b19bef890ddb7e1..f8c37763069c89acd642ad1f625cde3466e5be3d 100644 (file)
--- a/src/soc/fu/ldst/pipe_data.py
+++ b/src/soc/fu/ldst/pipe_data.py
@@ -16,6 +16,8 @@ class LDSTInputData(FUBaseData):
 
 
 class LDSTOutputData(FUBaseData):
+    # these need to tie up with LDSTCompUnit.get_out index numbers
+    # LDSTCompUnit is unusual in that it's non-standard to RegSpecAPI
     regspec = [('INT', 'o', '0:63'),   # RT
                ('INT', 'o1', '0:63'),  # RA (effective address, update mode)
                # TODO, later ('CR', 'cr_a', '0:3'),

diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py
index ebc529fcada9f0a3b60d2fee463890f477955f21..4ac2e2847ccadc8db5c37600a0a5b5f50889512c 100644 (file)
--- a/src/soc/simple/test/test_issuer.py
+++ b/src/soc/simple/test/test_issuer.py
@@ -43,15 +43,15 @@ if __name__ == "__main__":
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))
-    suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(DivTestCases().test_data, svp64=svp64))
     # suite.addTest(TestRunner(AttnTestCase.test_data, svp64=svp64))
     suite.addTest(TestRunner(GeneralTestCases.test_data, svp64=svp64))
     suite.addTest(TestRunner(LDSTTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
-    suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(CRTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(ShiftRotTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(LogicalTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(ALUTestCase().test_data, svp64=svp64))
+    #suite.addTest(TestRunner(BranchTestCase().test_data, svp64=svp64))
     # suite.addTest(TestRunner(SPRTestCase.test_data, svp64=svp64))
 
     runner = unittest.TextTestRunner()