add orangecrab to list of supported boards

diff --git a/src/ls2.py b/src/ls2.py
index 50d69e1e5cf337642067fbb82b9a0a22c3c0ec75..d95335024946bfb3a423be65cfeb366309ed607e 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -283,7 +283,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         # set up clock request generator
         pod_bits = 25
-        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
+        if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', 'orangecrab']:
             if fpga in ['isim']:
                 pod_bits = 6
             self.crg = ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits)