reduce size of ilang file by a factor of FIVE

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 55cacd32c501d47d7c09d863d4bea7092b09ae8f..945911baec843addb1ada7ffcb88746d4ff8547a 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -920,18 +920,22 @@ class ICache(Elaboratable):
 #          end if;
 #      end loop;
         # Test if pending request is a hit on any way
-        for i in range(NUM_WAYS):
-            tagi = Signal(TAG_BITS, name="ti%d" % i)
-            comb += tagi.eq(read_tag(i, cache_tags[req_index]))
-            with m.If(i_in.req &
-                      (cache_valid_bits[req_index][i] |
-                       ((r.state == State.WAIT_ACK)
-                        & (req_index == r.store_index)
-                        & (i == r.store_way)
-                        & r.rows_valid[req_row % ROW_PER_LINE]))):
-                with m.If(tagi == req_tag):
-                    comb += hit_way.eq(i)
-                    comb += is_hit.eq(1)
+        with m.If(i_in.req):
+            cvb = Signal(NUM_WAYS)
+            ctag = Signal(TAG_RAM_WIDTH)
+            comb += ctag.eq(cache_tags[req_index])
+            comb += cvb.eq(cache_valid_bits[req_index])
+            for i in range(NUM_WAYS):
+                tagi = Signal(TAG_BITS, name="ti%d" % i)
+                comb += tagi.eq(read_tag(i, ctag))
+                with m.If(cvb[i] |
+                           ((r.state == State.WAIT_ACK)
+                            & (req_index == r.store_index)
+                            & (i == r.store_way)
+                            & r.rows_valid[req_row % ROW_PER_LINE])):
+                    with m.If(tagi == req_tag):
+                        comb += hit_way.eq(i)
+                        comb += is_hit.eq(1)
 
 #      -- Generate the "hit" and "miss" signals
 #       -- for the synchronous blocks