add debug prints in old simulator

diff --git a/src/soc/experiment/cscore.py b/src/soc/experiment/cscore.py
index ea6bd32082e226da15312050cbbe6c66e608ae59..b661847823934bcb734ee8f60834189b5faec23f 100644 (file)
--- a/src/soc/experiment/cscore.py
+++ b/src/soc/experiment/cscore.py
@@ -265,8 +265,12 @@ class RegSim:
         src2 = self.regs[src2]
         if op == IADD:
             val = (src1 + src2) & ((1 << (self.rwidth))-1)
+            print ("RegSim op: ADD", hex(src1), hex(src2), hex(val))
         elif op == ISUB:
             val = (src1 - src2) & ((1 << (self.rwidth))-1)
+            print ("RegSim op: SUB", hex(src1), hex(src2), hex(val))
+        else:
+            print ("RegSim op: UNSUPPORTED", op)
         self.regs[dest] = val
 
     def setval(self, dest, val):