hdl.dsl: error on Elif immediately nested in an If.

I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 12081aca9caffa9e1752630cbb997c9000bd509d..fd207741d15745879e20b15f79927f001c738e1c 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -249,7 +249,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         cond = self._check_signed_cond(cond)
         src_loc = tracer.get_src_loc(src_loc_at=1)
         if_data = self._get_ctrl("If")
-        if if_data is None:
+        if if_data is None or len(if_data["tests"]) == 0:
             raise SyntaxError("Elif without preceding If")
         try:
             _outer_case, self._statements = self._statements, []

diff --git a/tests/test_hdl_dsl.py b/tests/test_hdl_dsl.py
index 8ec1be718c155a75b3a2e14937884bbf72a9ace8..6c5f1178f87b06089ff7be38e30f6f08cafda422 100644 (file)
--- a/tests/test_hdl_dsl.py
+++ b/tests/test_hdl_dsl.py
@@ -266,6 +266,14 @@ class DSLTestCase(FHDLTestCase):
             with m.Elif(self.s2):
                 pass
 
+    def test_Elif_wrong_nested(self):
+        m = Module()
+        with m.If(self.s1):
+            with self.assertRaisesRegex(SyntaxError,
+                    r"^Elif without preceding If$"):
+                with m.Elif(self.s2):
+                    pass
+
     def test_Else_wrong(self):
         m = Module()
         with self.assertRaisesRegex(SyntaxError,