reduce CSR data width to 8 as an experiment

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index 475314f2f01d7de0a40a9b21cfe3b59b9943fb8d..460a85d549c6973800ec35c05d39b208dfc40484 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -96,7 +96,7 @@ class LibreSoCSim(SoCSDRAM):
             #bus_data_width           = 64,
             csr_address_width        = 12, # limit to 0x4000
             cpu_variant              = variant,
-            csr_data_width            = 32,
+            csr_data_width            = 8,
             l2_size             = 0,
             uart_name                = "sim",
             with_sdram               = with_sdram,