add bugreport link to mmu

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index e062ceb9332174760d81bbacbc1d65f70158ad9e..b3d09b4e7e36bf1b0c7ff09995f15b40ac8a209a 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -1,3 +1,9 @@
+"""
+Based on microwatt mmu.vhdl
+
+* https://bugs.libre-soc.org/show_bug.cgi?id=491
+"""
+
 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
 from nmigen import Record, Memory
 from nmigen import Const