derive from Elaboratable

diff --git a/src/TLB/AddressEncoder.py b/src/TLB/AddressEncoder.py
index 4c4b8d763ce07914d978ffea6289926d5e233214..128f2c97ba633c088f9a7c90805307e7239b76c7 100644 (file)
--- a/src/TLB/AddressEncoder.py
+++ b/src/TLB/AddressEncoder.py
@@ -1,7 +1,7 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.lib.coding import Encoder, PriorityEncoder
 
-class AddressEncoder():
+class AddressEncoder(Elaboratable):
     """Address Encoder
 
        The purpose of this module is to take in a vector and

diff --git a/src/TLB/Cam.py b/src/TLB/Cam.py
index 46ba27bd8e3fd9e5f3b94b8fbe2165871ae29e6e..e7d901ff2ae9d4683f2d08d7393bf9fe7a4a203b 100644 (file)
--- a/src/TLB/Cam.py
+++ b/src/TLB/Cam.py
@@ -1,4 +1,4 @@
-from nmigen import Array, Cat, Module, Signal
+from nmigen import Array, Cat, Module, Signal, Elaboratable
 from nmigen.lib.coding import Decoder
 from nmigen.cli import main #, verilog
 
@@ -6,7 +6,7 @@ from .CamEntry import CamEntry
 from .AddressEncoder import AddressEncoder
 
 
-class Cam():
+class Cam(Elaboratable):
     """ Content Addressable Memory (CAM)
 
         The purpose of this module is to quickly look up whether an

diff --git a/src/TLB/CamEntry.py b/src/TLB/CamEntry.py
index 73081ce5250d0dac1ad240421ce11eb21b680ac6..b1d930828af890ad76a9df198ff1712ae472d20f 100644 (file)
--- a/src/TLB/CamEntry.py
+++ b/src/TLB/CamEntry.py
@@ -1,6 +1,7 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 
-class CamEntry:
+
+class CamEntry(Elaboratable):
     """ Content Addressable Memory (CAM) Entry
 
         The purpose of this module is to represent an entry within a CAM.

diff --git a/src/TLB/PermissionValidator.py b/src/TLB/PermissionValidator.py
index e3058cb24cd4cee0ac43a42583af5949ff0ee3b8..0107c0e9ca6700162a68f88d2d413bef74cf2d0e 100644 (file)
--- a/src/TLB/PermissionValidator.py
+++ b/src/TLB/PermissionValidator.py
@@ -1,9 +1,10 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main
 
-from .PteEntry import PteEntry
+from TLB.PteEntry import PteEntry
 
-class PermissionValidator():
+
+class PermissionValidator(Elaboratable):
     """ The purpose of this Module is to check the Permissions of a given PTE
         against the requested access permissions.
 

diff --git a/src/TLB/PteEntry.py b/src/TLB/PteEntry.py
index c07054576f1e30a1c781624263fe9956fdb4a279..73ea9220a720ce1ff0e56c0763d12dae06fc4bb9 100644 (file)
--- a/src/TLB/PteEntry.py
+++ b/src/TLB/PteEntry.py
@@ -1,7 +1,8 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main
 
-class PteEntry():
+
+class PteEntry(Elaboratable):
     """ The purpose of this Module is to  centralize the parsing of Page
         Table Entries (PTE) into one module to prevent common mistakes
         and duplication of code. The control bits are parsed out for
@@ -63,4 +64,4 @@ class PteEntry():
         ]
         m.d.comb += self.asid.eq(self.i[self.asid_start:self.asid_end])
         m.d.comb += self.pte.eq(self.i[0:self.asid_start])
-        return m
\ No newline at end of file
+        return m