projects
/
ieee754fpu.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
6e24978
)
update to nmutil Memory API
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 2 Aug 2019 00:50:22 +0000
(
01:50
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 2 Aug 2019 00:50:22 +0000
(
01:50
+0100)
src/nmutil/queue.py
patch
|
blob
|
history
diff --git
a/src/nmutil/queue.py
b/src/nmutil/queue.py
index 9407e5e0007356db40bd2e6b433d425899907fd6..069aa22cc33d8507a0644157e70bf0a39abbf450 100644
(file)
--- a/
src/nmutil/queue.py
+++ b/
src/nmutil/queue.py
@@
-62,7
+62,7
@@
class Queue(FIFOInterface, Elaboratable):
# set up an SRAM. XXX bug in Memory: cannot create SRAM of depth 1
ram = Memory(self.width, self.depth if self.depth > 1 else 2)
- m.submodules.ram_read = ram_read = ram.read_port(
synchronous=False
)
+ m.submodules.ram_read = ram_read = ram.read_port(
domain="comb"
)
m.submodules.ram_write = ram_write = ram.write_port()
# convenience names, for people familiar with ready/valid terminology