missing a fastregs write-port

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 895739a1390543bdfdb0736b06ecb71b5386c2b5..5ba3b91727bb357e1c87a762ebde1a2df6ffc8b0 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -63,7 +63,8 @@ class FastRegs(RegFileArray):
     def __init__(self):
         super().__init__(64, 8)
         self.w_ports = [self.write_port("dest1"),
-                        self.write_port("dest2")]
+                        self.write_port("dest2"),
+                        self.write_port("dest3")]
         self.r_ports = [self.read_port("src1"),
                         self.read_port("src2"),
                         self.read_port("src3")]