increase (double) address width in TstL0CacheBuffer

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index c356e29b36dae4823c4964573a9fe85b26441f3c..f42545d5a2c480919e00603080fe82e6440538ce 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -266,7 +266,7 @@ class L0CacheBuffer(Elaboratable):
 class TstL0CacheBuffer(Elaboratable):
     def __init__(self, n_units=3, regwid=16, addrwid=4, ifacetype='testpi'):
         pspec = TestMemPspec(ldst_ifacetype=ifacetype,
-                             addr_wid=addrwid,
+                             addr_wid=addrwid<<1,
                              mask_wid=8,
                              reg_wid=regwid)
         self.cmpi = ConfigMemoryPortInterface(pspec)