pass over atomic signals to dcache from loadstore.

does not do everything yet: load-quad for example is not included

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 228f9add0264da2877f3e67b22c14e3ec6e1c4bc..5ed6f8ebcffcae8956df4bb377aa852f666f52e3 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1708,7 +1708,7 @@ class DCache(Elaboratable):
 
         r1 = RegStage1("r1")
 
-        reservation = Reservation()
+        reservation = Reservation("rsrv")
 
         # Async signals on incoming request
         req_index    = Signal(INDEX_BITS)

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 7200540d3baa86b0ba24a23c67d87073b1378e63..034aaa01094739a6ad5d949c23f3fef2c549ae2e 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -129,6 +129,7 @@ class LoadStore1(PortInterfaceBase):
         self.busy          = Signal()
         self.wait_dcache   = Signal()
         self.wait_mmu      = Signal()
+        self.lrsc_misalign = Signal()
         #self.intr_vec     : integer range 0 to 16#fff#;
         #self.nia           = Signal(64)
         #self.srr1          = Signal(16)
@@ -170,6 +171,8 @@ class LoadStore1(PortInterfaceBase):
         # hmm, rather than add yet another argument to set_wr_addr
         # read direct from PortInterface
         m.d.comb += self.req.reserve.eq(self.pi.reserve) # atomic request
+        m.d.comb += self.req.atomic.eq(~self.lrsc_misalign)
+        m.d.comb += self.req.atomic_last.eq(~self.lrsc_misalign)
 
         return None
 
@@ -194,6 +197,8 @@ class LoadStore1(PortInterfaceBase):
         # hmm, rather than add yet another argument to set_rd_addr
         # read direct from PortInterface
         m.d.comb += self.req.reserve.eq(self.pi.reserve) # atomic request
+        m.d.comb += self.req.atomic.eq(~self.lrsc_misalign)
+        m.d.comb += self.req.atomic_last.eq(~self.lrsc_misalign)
 
         return None #FIXME return value
 
@@ -236,6 +241,10 @@ class LoadStore1(PortInterfaceBase):
         maddr = Signal(64)
         m.d.comb += maddr.eq(self.raddr)
 
+        # check for LR/SC misalignment, used in set_rd/wr_addr above
+        comb += self.lrsc_misalign.eq(((self.pi.data_len[0:3]-1) &
+                                        self.req.raddr[0:3]).bool())
+
         # create a blip (single pulse) on valid read/write request
         # this can be over-ridden in the FSM to get dcache to re-run
         # a request when MMU_LOOKUP completes.