add ports to TestMemory

diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 7c753a0d821435d1be4e840f46017a3a1187e95e..4821e21d3fcc9aa3b141717a8c9f19c7ab3284ee 100644 (file)
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -17,3 +17,14 @@ class TestMemory(Elaboratable):
         m.submodules.rdport = self.rdport
         m.submodules.wrport = self.wrport
         return m
+
+    def __iter__(self):
+        yield self.rdport.addr
+        yield self.rdport.data
+        yield self.rdport.en
+        yield self.wrport.addr
+        yield self.wrport.data
+        yield self.wrport.en
+
+    def ports(self):
+        return list(self)