Correct setup for experiment9/freepdk_c4m45, restrict to 6 metals.

diff --git a/experiments9/freepdk_c4m45/Makefile b/experiments9/freepdk_c4m45/Makefile
index 134f59b95f4b4ebd4ea4bc9b216b1766d971f94a..1a2db134c5ebc6c427d6dbd3fa432fcdc28cc86b 100755 (executable)
--- a/experiments9/freepdk_c4m45/Makefile
+++ b/experiments9/freepdk_c4m45/Makefile
@@ -1,6 +1,6 @@
             # use git submodule version of c4m-pdk-freepdk45
            # remember to do "git submodule update --init --remote
-            PDKMASTER_TOP = $(shell pwd)/../../../c4m-pdk-freepdk45
+            PDKMASTER_TOP = $(shell pwd)/../../c4m-pdk-freepdk45
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = FreePDK_C4M45

diff --git a/experiments9/freepdk_c4m45/coriolis2/settings.py b/experiments9/freepdk_c4m45/coriolis2/settings.py
index cc10a52e3b3968b41ae7b630624b0a6f5ed14398..c0ddc5c1995f0f5d5cfcbe3b89b20ec002939205 100644 (file)
--- a/experiments9/freepdk_c4m45/coriolis2/settings.py
+++ b/experiments9/freepdk_c4m45/coriolis2/settings.py
@@ -18,7 +18,7 @@ if not NdaDirectory:
 helpers.setNdaTopDir( NdaDirectory )
 
 import Cfg
-from   CRL     import AllianceFramework
+from   CRL     import AllianceFramework, RoutingLayerGauge
 from   helpers import overlay, l, u, n
 from   NDA.node45.freepdk45_c4m import techno, FlexLib, LibreSOCIO
 
@@ -38,7 +38,9 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.misc.verboseLevel2       = True
     cfg.etesian.graphics         = 3
     cfg.etesian.spaceMargin      = 0.10
+    cfg.anabatic.topRoutingLayer = 'metal6'
     cfg.katana.eventsLimit       = 4000000
     af  = AllianceFramework.get()
+    af.getRoutingGauge('FlexLib').getLayerGauge( 5 ).setType( RoutingLayerGauge.PowerSupply )
     env = af.getEnvironment()
     env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )

diff --git a/experiments9/freepdk_c4m45/doDesign.py b/experiments9/freepdk_c4m45/doDesign.py
index 4c83e1f79a7e8ec44f4de31b48220a401551611a..e1a04aa921da94b345b379434d91bf800eec511b 100644 (file)
--- a/experiments9/freepdk_c4m45/doDesign.py
+++ b/experiments9/freepdk_c4m45/doDesign.py
@@ -135,8 +135,8 @@ def scriptMain (**kw):
    #helpers.setTraceLevel( 550 )
    #Breakpoint.setStopLevel( 100 )
     rvalue     = True
-    coreSize   = u(1500.0)
-    chipSize   = u(3400.0)
+    coreSize   = u(375*4.0)
+    chipSize   = u(32*90.0 + 2*214.0)
     #coreSize   = u(17*90.0)
     #coreSize   = u(59*90.0)
     #chipBorder = u(2*214.0 + 10*13.0) + u(20*90.0)