PHYSICAL_SYNTHESIS = Coriolis
DESIGN_KIT = cmos45
YOSYS_FLATTEN = No
- YOSYS_BLACKBOXES = spblock_512w64b8w pll
+ YOSYS_BLACKBOXES = pll spblock_512w64b8w
# YOSYS_SET_TOP = Yes
CHIP = chip
CORE = ls180
cp non_generated/full_core_4_4ksram_litex_ls180.v litex_ls180.v
cp non_generated/full_core_4_4ksram_libresoc.v libresoc.v
cp non_generated/spblock*.v* .
+cp non_generated/pll.v .
touch mem.init
touch mem_1.init
touch mem_2.init
touch mem_4.init
touch mem_5.init
-
# make the vst from verilog
make vst