virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
}
+static void virgl_memory_barrier(struct pipe_context *ctx,
+ unsigned flags)
+{
+ struct virgl_context *vctx = virgl_context(ctx);
+ struct virgl_screen *rs = virgl_screen(ctx->screen);
+
+ if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_MEMORY_BARRIER))
+ return;
+ virgl_encode_memory_barrier(vctx, flags);
+}
+
static void
virgl_context_destroy( struct pipe_context *ctx )
{
vctx->base.set_shader_buffers = virgl_set_shader_buffers;
vctx->base.set_shader_images = virgl_set_shader_images;
+ vctx->base.memory_barrier = virgl_memory_barrier;
+
virgl_init_context_resource_functions(&vctx->base);
virgl_init_query_functions(vctx);
virgl_init_so_functions(vctx);
}
return 0;
}
+
+int virgl_encode_memory_barrier(struct virgl_context *ctx,
+ unsigned flags)
+{
+ virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_MEMORY_BARRIER, 0, 1));
+ virgl_encoder_write_dword(ctx->cbuf, flags);
+ return 0;
+}
enum pipe_shader_type shader,
unsigned start_slot, unsigned count,
const struct pipe_image_view *images);
+int virgl_encode_memory_barrier(struct virgl_context *ctx,
+ unsigned flags);
#endif
#define VIRGL_CAP_COPY_IMAGE (1 << 3)
#define VIRGL_CAP_TGSI_PRECISE (1 << 4)
#define VIRGL_CAP_TXQS (1 << 5)
+#define VIRGL_CAP_MEMORY_BARRIER (1 << 6)
#define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
#define VIRGL_BIND_RENDER_TARGET (1 << 1)
VIRGL_CCMD_SET_MIN_SAMPLES,
VIRGL_CCMD_SET_SHADER_BUFFERS,
VIRGL_CCMD_SET_SHADER_IMAGES,
+ VIRGL_CCMD_MEMORY_BARRIER,
};
/*
#define VIRGL_SET_SHADER_IMAGE_LEVEL_SIZE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 6)
#define VIRGL_SET_SHADER_IMAGE_RES_HANDLE(x) ((x) * VIRGL_SET_SHADER_IMAGE_ELEMENT_SIZE + 7)
+/* memory barrier */
+#define VIRGL_MEMORY_BARRIER_SIZE 1
+#define VIRGL_MEMORY_BARRIER_FLAGS 1
+
#endif