virgl: add TXQS support
authorDave Airlie <airlied@redhat.com>
Thu, 19 Jul 2018 23:18:04 +0000 (09:18 +1000)
committerDave Airlie <airlied@redhat.com>
Tue, 31 Jul 2018 22:02:32 +0000 (08:02 +1000)
Reviwed-by: Gert Wollny <gert.wollny@collabora.com>
src/gallium/drivers/virgl/virgl_hw.h
src/gallium/drivers/virgl/virgl_screen.c

index aa6d8f8fe4b2e0f97e05f5508723fe7f5cad96da..01baf05e6d473d8b064a9b6d8cbf4dad5d515d26 100644 (file)
@@ -204,6 +204,7 @@ enum virgl_formats {
 #define VIRGL_CAP_SET_MIN_SAMPLES      (1 << 2)
 #define VIRGL_CAP_COPY_IMAGE           (1 << 3)
 #define VIRGL_CAP_TGSI_PRECISE         (1 << 4)
+#define VIRGL_CAP_TXQS                 (1 << 5)
 
 #define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
 #define VIRGL_BIND_RENDER_TARGET (1 << 1)
index 1c94603a2dce73f8374d1d39ea295f3a842b8c5c..01e8eaec72085cac6d38e9392a2173eb7463b70d 100644 (file)
@@ -223,6 +223,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return vscreen->caps.caps.v2.max_vertex_attrib_stride;
    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
       return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_COPY_IMAGE;
+   case PIPE_CAP_TGSI_TXQS:
+      return vscreen->caps.caps.v2.capability_bits & VIRGL_CAP_TXQS;
    case PIPE_CAP_TEXTURE_GATHER_SM5:
    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
    case PIPE_CAP_FAKE_SW_MSAA:
@@ -238,7 +240,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
    case PIPE_CAP_DEPTH_BOUNDS_TEST:
-   case PIPE_CAP_TGSI_TXQS:
    case PIPE_CAP_SHAREABLE_SHADERS:
    case PIPE_CAP_CLEAR_TEXTURE:
    case PIPE_CAP_DRAW_PARAMETERS: