do not set sv_changed

diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py
index 80c8febd64436d7a7c864a078a8a0cd9f4282c05..9c9bdf208c8c491906a6dcbfc5acf6092b7ac91a 100644 (file)
--- a/src/soc/decoder/isa/radixmmu.py
+++ b/src/soc/decoder/isa/radixmmu.py
@@ -220,7 +220,7 @@ class RADIX:
     def __init__(self, mem, caller):
         self.mem = mem
         self.caller = caller
-        if(caller):
+        if caller is not None:
             self.dsisr = self.caller.spr["DSISR"]
             self.dar   = self.caller.spr["DAR"]
             self.pidr  = self.caller.spr["PIDR"]

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 482d364080f9514e6f86ad0ad6c524ed05abb773..aaed35085c3f407976ce3e1cb36d2e0c05173cd7 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -595,14 +595,12 @@ class TestIssuerInternal(Elaboratable):
                               (cur_srcstep != vl):
                             comb += update_svstate.eq(1)
                             comb += new_svstate.srcstep.eq(next_srcstep)
-                            sync += sv_changed.eq(1)
 
                     if not pred_dst_zero:
                         if (((1<<cur_dststep) & self.dstmask) == 0) and
                               (cur_dststep != vl):
                             comb += new_svstate.dststep.eq(next_dststep)
                             comb += update_svstate.eq(1)
-                            sync += sv_changed.eq(1)
 
                     if update_svstate:
                         m.next = "DECODE_SV"