correct address out_en name

diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py
index 3ab1f2b77e38042e25952051d2d37cb1e6bce421..6d73c896e459d9bd16a3b1af658fb4fb18e40d3d 100644 (file)
--- a/src/bsv/peripheral_gen/flexbus.py
+++ b/src/bsv/peripheral_gen/flexbus.py
@@ -52,7 +52,7 @@ class flexbus(PBase):
             ('tsiz', 'm_TSIZ'),
             ('ad_out', 'm_AD'),
             ('ad_in', 'm_din'),
-            ('ad_en', 'm_OE32n'),
+            ('ad_out_en', 'm_OE32n'),
         ]:
             ret.append(template.format(ps, ptype, n, stype))
         return '\n'.join(ret)