add icachemmu option to ISACaller

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index ba24f48fa54d0a9130ab30b6ce68594fc9469a8d..315db251fa97445244aac839fb330c1dc2ca78dc 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -424,7 +424,8 @@ class ISACaller:
                  disassembly=None,
                  initial_pc=0,
                  bigendian=False,
-                 mmu=False):
+                 mmu=False,
+                 icachemmu=False):
 
         self.bigendian = bigendian
         self.halted = False
@@ -472,7 +473,8 @@ class ISACaller:
         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
         if mmu:
             self.mem = RADIX(self.mem, self)
-            self.imem = RADIX(self.imem, self)
+            if icachemmu:
+                self.imem = RADIX(self.imem, self)
         self.pc = PC()
 
         # TODO, needed here: