tlbie, mtspr and mfspr test cases

diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index 9633ff312ae44671cb324124c14256dafcd9a7e8..98fdd45341fad0d12bd5fbc52b968f58cdc7bb89 100644 (file)
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -42,6 +42,31 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
+    def case_2_tlbie(self):
+        lst = ["tlbie 1,1,1,1,1"] # tlbie   RB,RS,RIC,PRS,R
+        initial_regs = [0] * 32
+        initial_mem = {}
+        self.add_case(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def case_3_mtspr(self):
+        lst = ["mtspr 720,1"] # mtspr PRTBL,r1
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1234
+        initial_mem = {}
+        self.add_case(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
+    def case_4_mfspr(self):
+        lst = ["mfspr 1,18", # mtspr r1,DSISR
+               "mfspr 2,19"] # mtspr r2,DAR
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x1234
+        initial_regs[2] = 0x3456
+        initial_mem = {}
+        self.add_case(Program(lst, bigendian), initial_regs,
+                             initial_mem=initial_mem)
+
 if __name__ == "__main__":
     svp64 = True
     if len(sys.argv) == 2: