fixing get_rd_sim_xer_ca, has to only read carry if available

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 514bb0bb28d3eac8c3e689992a80a4ffa87ecaf0..9ad8a46c4c0a98ebdb0d9fec8a7f5856a4c8ed76 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -40,7 +40,7 @@ class ALUTestRunner(TestRunner):
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
         yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ca(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
         yield from ALUHelpers.get_sim_xer_so(sim_o, sim, dec2)
 
         ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index b6ba048fdcdfd9f614c085dda901306a0a7d37cc..e61edb48586c800bfa44384c344f64bead89f0a3 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -3,7 +3,7 @@ Bugreports:
 * https://bugs.libre-soc.org/show_bug.cgi?id=361
 """
 
-from soc.decoder.power_enums import XER_bits
+from soc.decoder.power_enums import XER_bits, CryIn
 from soc.regfile.util import fast_reg_to_spr # HACK!
 
 
@@ -71,7 +71,7 @@ class ALUHelpers:
 
     def get_rd_sim_xer_ca(res, sim, dec2):
         cry_in = yield dec2.e.input_carry
-        if cry_in:
+        if cry_in == CryIn.CA.value:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = expected_carry | (expected_carry32 << 1)