increase timescale of icarus simulation

to cover the period for coldboot.bin to initialise DRAM and perform
read/write tests

diff --git a/simsoc.ys b/simsoc.ys
index 4bf15309728a120187f6cee41f2e5b25351d9096..1a7780ab3fa7431f80e29f22b97d43ae776f5817 100644 (file)
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -4,15 +4,18 @@ read_verilog  ../uart16550/rtl/verilog/uart_defines.v
 read_verilog  ../uart16550/rtl/verilog/uart_rfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_top.v
 read_verilog  ../uart16550/rtl/verilog/timescale.v
-read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
 read_verilog  ../uart16550/rtl/verilog/uart_sync_flops.v
-read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
 read_verilog  ../uart16550/rtl/verilog/uart_debug_if.v
 read_verilog  ../uart16550/rtl/verilog/uart_regs.v
+read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
+read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ./external_core_top.v
 
+setattr -mod -set keep 1 uart_transmitter
+setattr -mod -set keep 1 uart_receiver
+
 delete w:$verilog_initial_trigger
 proc_prune
 proc_clean

diff --git a/src/simsoctb.v b/src/simsoctb.v
index 5a5dd26fc68482d9aefc999d343191da70dba500..77e5035a99f9c9ec1fac652bbeae49708685bf18 100644 (file)
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -69,7 +69,7 @@ module simsoctb;
 
   // uart, LEDs, switches
   wire uart_tx ;
-  reg uart_rx = 0;
+  wire uart_rx;
   wire led_0;
   wire led_1;
   wire led_2;
@@ -150,7 +150,7 @@ module simsoctb;
   initial
     begin
       // run for a set time period then exit
-      #5000000;
+      #120000000;
 
       $finish;
     end