add new (experimental) ffmadds and ffmsubs, for FFT twin mul-accumulate

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index ea2a4a8d635a0a4eb754b67ee7df436a4a45eb25..1bcc1ac7f653b0ffecbc439a28f611df0c555acf 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -9,8 +9,8 @@
 
 A-Form
 
-* faddso FRT,FRA,FRB (Rc=0)
-* faddso. FRT,FRA,FRB (Rc=1)
+* ffadds FRT,FRA,FRB (Rc=0)
+* ffadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -28,8 +28,8 @@ Special Registers Altered:
 
 A-Form
 
-* faddo FRT,FRA,FRB (Rc=0)
-* faddo. FRT,FRA,FRB (Rc=1)
+* ffadd FRT,FRA,FRB (Rc=0)
+* ffadd. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -47,8 +47,8 @@ Special Registers Altered:
 
 A-Form
 
-* fsubso FRT,FRA,FRB (Rc=0)
-* fsubso. FRT,FRA,FRB (Rc=1)
+* ffsubs FRT,FRA,FRB (Rc=0)
+* ffsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -66,8 +66,8 @@ Special Registers Altered:
 
 A-Form
 
-* fsubo FRT,FRA,FRB (Rc=0)
-* fsubo. FRT,FRA,FRB (Rc=1)
+* ffsub FRT,FRA,FRB (Rc=0)
+* ffsub. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -85,8 +85,8 @@ Special Registers Altered:
 
 A-Form
 
-* fmulso FRT,FRA,FRC (Rc=0)
-* fmulso. FRT,FRA,FRC (Rc=1)
+* ffmuls FRT,FRA,FRC (Rc=0)
+* ffmuls. FRT,FRA,FRC (Rc=1)
 
 Pseudo-code:
 
@@ -104,8 +104,8 @@ Special Registers Altered:
 
 A-Form
 
-* fmulo FRT,FRA,FRC (Rc=0)
-* fmulo. FRT,FRA,FRC (Rc=1)
+* ffmul FRT,FRA,FRC (Rc=0)
+* ffmul. FRT,FRA,FRC (Rc=1)
 
 Pseudo-code:
 
@@ -123,8 +123,8 @@ Special Registers Altered:
 
 A-Form
 
-* fdivso FRT,FRA,FRB (Rc=0)
-* fdivso. FRT,FRA,FRB (Rc=1)
+* ffdivs FRT,FRA,FRB (Rc=0)
+* ffdivs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -142,8 +142,8 @@ Special Registers Altered:
 
 A-Form
 
-* fdivo FRT,FRA,FRB (Rc=0)
-* fdivo. FRT,FRA,FRB (Rc=1)
+* ffdiv FRT,FRA,FRB (Rc=0)
+* ffdiv. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -161,13 +161,13 @@ Special Registers Altered:
 
 A-Form
 
-* fmaddso FRT,FRA,FRC,FRB (Rc=0)
-* fmaddso. FRT,FRA,FRC,FRB (Rc=1)
+* ffmadds FRT,FRA,FRC,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
     FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
 
 Special Registers Altered:
 
@@ -180,13 +180,13 @@ Special Registers Altered:
 
 A-Form
 
-* fmsubso FRT,FRA,FRC,FRB (Rc=0)
-* fmsubso. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
     FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
 
 Special Registers Altered:
 
@@ -199,13 +199,13 @@ Special Registers Altered:
 
 A-Form
 
-* fnmaddso FRT,FRA,FRC,FRB (Rc=0)
-* fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmadds FRT,FRA,FRC,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
     FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
 
 Special Registers Altered:
 
@@ -218,13 +218,13 @@ Special Registers Altered:
 
 A-Form
 
-* fnmsubso FRT,FRA,FRC,FRB (Rc=0)
-* fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
 
 Pseudo-code:
 
     FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
 
 Special Registers Altered:
 

diff --git a/openpower/isatables/LDSTRM-2P-1S1D.csv b/openpower/isatables/LDSTRM-2P-1S1D.csv
index 000bfcf88fc9bfa6e8f5de742ad77738b4eed831..51717dea5ccf46994801820d1f607f97a35ae50a 100644 (file)
--- a/openpower/isatables/LDSTRM-2P-1S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-1S1D.csv
@@ -5,5 +5,5 @@ lhz,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 lha,~SVP64BREV,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
 lfs,~SVP64BREV,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
 lfd,~SVP64BREV,2P,EXTRA3,d:FRT,s:RA,0,0,RA_OR_ZERO,0,0,FRT,0,0,0
-ld,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,RC,RT,0,0,0
-lwa,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,RC,RT,0,0,0
+ld,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0
+lwa,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,0

diff --git a/openpower/isatables/LDSTRM-2P-1S2D.csv b/openpower/isatables/LDSTRM-2P-1S2D.csv
index c48a18a9565ee58f395b284b1bcb5220ef217601..e353526824eb8da39806f6940d9e38ed87861415 100644 (file)
--- a/openpower/isatables/LDSTRM-2P-1S2D.csv
+++ b/openpower/isatables/LDSTRM-2P-1S2D.csv
@@ -5,4 +5,4 @@ lhzu,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
 lhau,~SVP64BREV,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA
 lfsu,~SVP64BREV,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,RA
 lfdu,~SVP64BREV,2P,EXTRA2,d:FRT,d:RA,s:RA,0,RA,0,0,FRT,0,0,RA
-ldu,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,RC,RT,0,0,RA
+ldu,,2P,EXTRA2,d:RT,d:RA,s:RA,0,RA_OR_ZERO,0,0,RT,0,0,RA

diff --git a/openpower/isatables/LDSTRM-2P-2S1D.csv b/openpower/isatables/LDSTRM-2P-2S1D.csv
index 9d489ad7379492fa9e98e4fbf3d0bea3eb6e782b..4bda8fed136daba9bdb1d0025202296580c0b7d1 100644 (file)
--- a/openpower/isatables/LDSTRM-2P-2S1D.csv
+++ b/openpower/isatables/LDSTRM-2P-2S1D.csv
@@ -20,14 +20,18 @@ lbzcix,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lfiwax,,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0
 ldcix,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,0
 lfiwzx,,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,RB,0,FRT,0,0,0
+lwz,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
+lbz,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
 stwu,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
 stbu,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+lhz,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
+lha,SVP64BREV,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
 sthu,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
+lfs,SVP64BREV,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,FRT,0,0,0
+lfd,SVP64BREV,2P,EXTRA2,d:FRT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,FRT,0,0,0
 stfsu,,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,RA
 stfdu,,2P,EXTRA2,d:RA,s:FRS,s:RA,0,RA,0,FRS,0,0,0,RA
 stdu,,2P,EXTRA2,d:RA,s:RS,s:RA,0,RA_OR_ZERO,0,RS,0,0,0,RA
-ld,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
-lwa,,2P,EXTRA2,d:RT,s:RA,s:RB,0,RA_OR_ZERO,0,RC,RT,0,0,0
 ldux,,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
 lwzux,,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
 lbzux,,2P,EXTRA2,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA

diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv
index f354c96c5f57a9f220917c0e4061fcae2c36ca40..46c62827a957c916a2f6ab84cf3fa7a22f2ed673 100644 (file)
--- a/openpower/isatables/RM-1P-3S1D.csv
+++ b/openpower/isatables/RM-1P-3S1D.csv
@@ -31,6 +31,10 @@ isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0
+ffmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+ffmadds,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+ffnmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
+ffnmadds,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
 fmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
 fmadds,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0
 fnmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0

diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index b72cef1a4779392e71a30a4a2f5ce7c4dd6ffa0b..0891f0a33b7ef62476c8f10911d97c46013ef574 100644 (file)
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -8,11 +8,11 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 -----11000,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fres,A,
 -----11001,FPU,OP_FPOP,FRA,NONE,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmuls,A,
 -----11010,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,frsqrtes,A,
------11100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,A,~SVP64FFT
------11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,A,~SVP64FFT
------11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,A,~SVP64FFT
------11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,A,~SVP64FFT
------11100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubso,A,SVP64FFT
------11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmaddso,A,SVP64FFT
------11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubso,A,SVP64FFT
------11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmaddso,A,SVP64FFT
+-----11100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmsubs,A,
+-----11101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fmadds,A,
+-----11110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmsubs,A,
+-----11111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,fnmadds,A,
+-----00100,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffmsubs,A,
+-----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffmadds,A,
+-----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmsubs,A,
+-----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,ffnmadds,A,

diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py
index 802a3e3528045ba98a35d737a12bf245470c4b89..b219767cebe0726237a5e5fee422049b1593d2ec 100644 (file)
--- a/src/openpower/decoder/helpers.py
+++ b/src/openpower/decoder/helpers.py
@@ -323,9 +323,11 @@ def FPMULADD32(FRA, FRC, FRB, mulsign, addsign):
             result = -(float(FRA) * float(FRC) + float(FRB))  # fnmadds
     elif addsign == 0:
         result = 0.0
-    log ("FPMULADD32", FRA, FRB, FRC,
-                       float(FRA), float(FRB), float(FRC),
-                       result)
+    log ("FPMULADD32 FRA FRC FRB", FRA, FRC, FRB)
+    log ("      FRA", float(FRA))
+    log ("      FRC", float(FRC))
+    log ("      FRB", float(FRB))
+    log ("      (FRA*FRC)+FRB=", mulsign, addsign, result)
     cvt = fp64toselectable(result)
     cvt = DOUBLE2SINGLE(cvt)
     log ("      cvt", cvt)

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 3e9be7261807908b91424e159517976c298f5158..b870ebe7bd860845926f136abedcc4f93928c8e3 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -491,15 +491,15 @@ def get_pdecode_idx_out(dec2, name):
 # TODO, really should just be using PowerDecoder2
 def get_pdecode_idx_out2(dec2, name):
     # check first if register is activated for write
-    out_ok = yield dec2.e.write_ea.ok
-    if not out_ok:
-        return None, False
-
     op = dec2.dec.op
     out_sel = yield op.out_sel
     out = yield dec2.e.write_ea.data
     o_isvec = yield dec2.o2_isvec
-    log ("get_pdecode_idx_out2", name, out_sel, out, o_isvec)
+    out_ok = yield dec2.e.write_ea.ok
+    log ("get_pdecode_idx_out2", name, out_sel, out, out_ok, o_isvec)
+    if not out_ok:
+        return None, False
+
     if name == 'RA':
         if hasattr(op, "upd"):
             # update mode LD/ST uses read-reg A also as an output
@@ -509,6 +509,13 @@ def get_pdecode_idx_out2(dec2, name):
                                            out, o_isvec)
             if upd == LDSTMode.update.value:
                 return out, o_isvec
+    if name == 'FRS':
+        int_op = yield dec2.dec.op.internal_op
+        fft_en = yield dec2.use_svp64_fft
+        if int_op == MicrOp.OP_FP_MADD.value and fft_en:
+            log ("get_pdecode_idx_out2", out_sel, OutSel.FRS.value,
+                                           out, o_isvec)
+            return out, o_isvec
     return None, False
 
 
@@ -877,6 +884,7 @@ class ISACaller:
                               pfx.insn[7].value == 0b1 and
                               pfx.insn[9].value == 0b1)
         self.pc.update_nia(self.is_svp64_mode)
+        yield self.dec2.is_svp64_mode.eq(self.is_svp64_mode) # set SVP64 decode
         self.namespace['NIA'] = self.pc.NIA
         self.namespace['SVSTATE'] = self.svstate.spr
         if not self.is_svp64_mode:
@@ -1045,6 +1053,11 @@ class ISACaller:
             illegal = False
             name = 'setvl'
 
+        # sigh also deal with ffmadds not being supported by binutils (.long)
+        if asmop == 'ffmadds':
+            illegal = False
+            name = 'ffmadds'
+
         if illegal:
             print("illegal", name, asmop)
             self.call_trap(0x700, PIb.ILLEG)
@@ -1080,9 +1093,10 @@ class ISACaller:
             srcstep = self.svstate.srcstep.asint(msb0=True)
             dststep = self.svstate.dststep.asint(msb0=True)
             sv_a_nz = yield self.dec2.sv_a_nz
+            fft_mode = yield self.dec2.use_svp64_fft
             in1 = yield self.dec2.e.read_reg1.data
-            log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
-                    vl, srcstep, dststep, sv_a_nz, in1)
+            log ("SVP64: VL, srcstep, dststep, sv_a_nz, in1 fft",
+                    vl, srcstep, dststep, sv_a_nz, in1, fft_mode)
 
         # get predicate mask
         srcmask = dstmask = 0xffff_ffff_ffff_ffff

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 5f9f577c59ff58df7c715bd19409093a61a2dd17..3bce7e8473b67d341aaccc438d6a04a2e2a7820e 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -776,6 +776,7 @@ if __name__ == '__main__':
                      }
         pdecode = create_pdecode(name="rowsub",
                                  col_subset={'opcode', 'function_unit',
+                                              'asmcode',
                                              'in2_sel', 'in3_sel'},
                                  row_subset=rowsubsetfn,
                                  include_fp=True,

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 073038402b7786203f6abe819324fc20b3f42a65..ccf9fef1835521a761ed17bc7e422ae0d51ef5ec 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1022,8 +1022,8 @@ class PowerDecodeSubset(Elaboratable):
                 # if bit-reverse mode requested
                 bitrev = rm_dec.ldstmode == SVP64LDSTmode.BITREVERSE
                 comb += self.use_svp64_ldst_dec.eq(bitrev)
-                # if SVP64 FFT mode enabled (overload OE ha ha)
-                comb += self.use_svp64_fft.eq(self.dec.OE)
+            # if SVP64 FFT mode enabled
+            comb += self.use_svp64_fft.eq(self.is_svp64_mode)
 
         # decoded/selected instruction flags
         comb += self.do_copy("data_len", self.op_get("ldst_len"))
@@ -1300,6 +1300,8 @@ class PowerDecode2(PowerDecodeSubset):
                         comb += to_reg.data.eq(vl+svdec.reg_out+(vl-1-dststep))
                     with m.Else():
                         comb += to_reg.data.eq(vl+dststep+svdec.reg_out)
+                with m.Else():
+                    comb += to_reg.data.eq(vl+svdec.reg_out)
                 # ... but write to *second* output
                 comb += self.o2_isvec.eq(svdec.isvec)
                 comb += o2_svdec.idx.eq(self.op_get("sv_out"))

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index ab292833ba4137caeff44961d53567b5eb60eb6a..bf5738997b4b08eae72f732b458e0fd24f73cb6f 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -241,6 +241,7 @@ _insns = [
     "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
     "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
     "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
+    "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
     "hrfid", "icbi", "icbt", "isel", "isync",
@@ -434,6 +435,7 @@ class OutSel(Enum):
     SPR = 3
     RT_OR_ZERO = 4
     FRT = 5
+    FRS = 6
 
 
 @unique

diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index dae18c6cf4148a16bb01601bdb9226b7613e7336..ed9fae793903fab942c89f0ec2feab218634ef40 100644 (file)
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -24,7 +24,7 @@ import ast
 # Helper function
 
 regs = ['RA', 'RS', 'RB', 'RC', 'RT']
-fregs = ['FRA', 'FRS', 'FRB', 'FRC', 'FRT']
+fregs = ['FRA', 'FRS', 'FRB', 'FRC', 'FRT', 'FRS']
 
 def Assign(autoassign, assignname, left, right, iea_mode):
     names = []

diff --git a/src/openpower/decoder/pseudo/pywriter.py b/src/openpower/decoder/pseudo/pywriter.py
index 67a4cbc67f9c37a367f22165e91f9cf16a796550..11a30e39a5a144e7396b2b68dbb66d4deb466d24 100644 (file)
--- a/src/openpower/decoder/pseudo/pywriter.py
+++ b/src/openpower/decoder/pseudo/pywriter.py
@@ -67,7 +67,8 @@ class PyISAWriter(ISA):
             iinf = ''
             # write headers: FP gets extra imports
             f.write(header)  # write out header
-            if pagename.startswith("fp"):
+            if (pagename.startswith("fp") or
+                pagename.startswith("svfp")):
                 f.write(fpheader)
             f.write("class %s:\n" % pagename)
 

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index cb9c904c1269563174b25a7206ba6f18371bb824..64888594edca1f737010a5f7faa7335f03083a82 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -791,7 +791,19 @@ class SVP64Asm:
         rc = '.' if rc_mode else ''
         yield ".long 0x%x" % svp64_prefix.insn.value
         log(v30b_newfields)
-        yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
+        # argh, sv.fmaddso etc. need to be done manually
+        if v30b_op == 'ffmadds':
+            opcode = 59 << (32-6)    # bits 0..6 (MSB0)
+            opcode |= int(v30b_newfields[0]) << (32-11) # FRT
+            opcode |= int(v30b_newfields[1]) << (32-16) # FRA
+            opcode |= int(v30b_newfields[2]) << (32-21) # FRB
+            opcode |= int(v30b_newfields[3]) << (32-26) # FRC
+            opcode |= 5 << (32-31)   # bits 26-30
+            if rc:
+                opcode |= 1  # Rc, bit 31.
+            yield ".long 0x%x" % opcode
+        else:
+            yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
         log ("new v3.0B fields", v30b_op, v30b_newfields)
 
     def translate(self, lst):
@@ -938,8 +950,9 @@ if __name__ == '__main__':
     lst = [
              'sv.addi win2.v, win.v, -1',
              'sv.add./mrr 5.v, 2.v, 1.v',
-             'sv.lhzbr 5.v, 11(9.v), 15',
-             'sv.lwzbr 5.v, 11(9.v), 15',
+             #'sv.lhzbr 5.v, 11(9.v), 15',
+             #'sv.lwzbr 5.v, 11(9.v), 15',
+             'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
     ]
     isa = SVP64Asm(lst, macros=macros)
     print ("list", list(isa))