add new (experimental) ffmadds and ffmsubs, for FFT twin mul-accumulate
[openpower-isa.git] / src / openpower / sv / trans / svp64.py
2021-06-27 Luke Kenneth Casso... add new (experimental) ffmadds and ffmsubs, for FFT...
2021-06-26 Luke Kenneth Casso... add LD bit-reversed unit test
2021-06-25 Luke Kenneth Casso... identify SVP64 LD bit-reverse pattern as pseudo-assembler
2021-06-23 Luke Kenneth Casso... add start of bit-reverse mode for LD/ST to SVP64 encode...
2021-06-19 Luke Kenneth Casso... add mapreduce "reverse gear" unit tests
2021-06-14 Luke Kenneth Casso... recognise setvl instruction during SVP64 translation
2021-06-14 Luke Kenneth Casso... whoops forgot format-to-format conversion
2021-06-14 Luke Kenneth Casso... series of text macro formats to look for: x.v, x.s (x)
2021-06-14 Luke Kenneth Casso... add basic "macro" (.set) support to SVP64Asm
2021-06-09 Luke Kenneth Casso... add what might turn out to be only what is needed to...
2021-05-30 Luke Kenneth Casso... add "normal" element-strided LD/ST decode/support to...
2021-05-23 Luke Kenneth Casso... read all lines in advance, in case of in-place overwrite
2021-05-23 Luke Kenneth Casso... add svp64 assembler "processor" commandline for replaci...
2021-05-19 Luke Kenneth Casso... comments for SVP64 ASM LD/ST-with-update duplicate RA
2021-05-19 Luke Kenneth Casso... add silent log debug option, if SILENCELOG env var...
2021-05-19 Luke Kenneth Casso... resolve merge conflicts, effectively reverting "verbose...
2021-05-19 Lauri KasanenStop spamming the world whenever PowerDecoder is fired up
2021-05-18 Luke Kenneth Casso... add beginning support for SVP64 IEEE754 FP
2021-04-23 Luke Kenneth Casso... resolving imports changing over
2021-04-23 Luke Kenneth Casso... add SV records