move pagetable to external file

diff --git a/src/soc/experiment/test/pagetables.py b/src/soc/experiment/test/pagetables.py
new file mode 100644 (file)
index 0000000..53bc039
--- /dev/null
+++ b/src/soc/experiment/test/pagetables.py
@@ -0,0 +1,25 @@
+def b(x): # byte-reverse function
+    return int.from_bytes(x.to_bytes(8, byteorder='little'),
+                          byteorder='big', signed=False)
+
+test1 = {
+           0x10000:    # PARTITION_TABLE_2
+                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+           b(0x800000000100000b),
+
+           0x30000:     # RADIX_ROOT_PTE
+                        # V = 1 L = 0 NLB = 0x400 NLS = 9
+           b(0x8000000000040009),
+
+           0x40000:     # RADIX_SECOND_LEVEL
+                        # V = 1 L = 1 SW = 0 RPN = 0
+                        # R = 1 C = 1 ATT = 0 EAA 0x7
+           b(0xc000000000000183),
+
+           0x1000000:   # PROCESS_TABLE_3
+                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+           b(0x40000000000300ad),
+
+           #0x10004: 0
+
+}

diff --git a/src/soc/experiment/test/test_dcbz_pi.py b/src/soc/experiment/test/test_dcbz_pi.py
index 45b8772859de4c7aab5872f0d345030621d80da9..b3e531d98133749f9462baff963855f38cfe4ede 100644 (file)
--- a/src/soc/experiment/test/test_dcbz_pi.py
+++ b/src/soc/experiment/test/test_dcbz_pi.py
@@ -17,15 +17,13 @@ from soc.config.loadstore import ConfigMemoryPortInterface
 
 from soc.fu.ldst.loadstore import LoadStore1
 from soc.experiment.mmu import MMU
+from soc.experiment.test import pagetables
 
 from nmigen.compat.sim import run_simulation
 
 
-stop = False
 
-def b(x): # byte-reverse function
-    return int.from_bytes(x.to_bytes(8, byteorder='little'),
-                          byteorder='big', signed=False)
+stop = False
 
 def wb_get(wb, mem):
     """simulator process for getting memory load requests
@@ -145,27 +143,7 @@ def test_dcbz_addr_100e0():
 
     m, cmpi = setup_mmu()
 
-    mem = {
-           0x10000:    # PARTITION_TABLE_2
-                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
-           b(0x800000000100000b),
-
-           0x30000:     # RADIX_ROOT_PTE
-                        # V = 1 L = 0 NLB = 0x400 NLS = 9
-           b(0x8000000000040009),
-
-           0x40000:     # RADIX_SECOND_LEVEL
-                        # V = 1 L = 1 SW = 0 RPN = 0
-                        # R = 1 C = 1 ATT = 0 EAA 0x7
-           b(0xc000000000000183),
-
-           0x1000000:   # PROCESS_TABLE_3
-                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
-           b(0x40000000000300ad),
-
-           0x10004: 0
-
-    }
+    mem = pagetables.test1
 
     # nmigen Simulation
     sim = Simulator(m)