whoops missed some cases in unit test changing ALUHelpers

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index b79b90995f80fce54681ca25d3f6f7ec0c171b6d..d093ad1b5c74b85a3f09b3d88033673c43897d82 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -191,7 +191,10 @@ class SPR(dict):
             if isinstance(key, SelectableInt):
                 key = key.value
             key = special_sprs.get(key, key)
-            info = spr_byname[key]
+            if isinstance(key, int):
+                info = spr_dict[key]
+            else:
+                info = spr_byname[key]
             if not isinstance(v, SelectableInt):
                 v = SelectableInt(v, info.length)
             self[key] = v

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index c2eb08885ad2e69582c32857a0f7684395a5c2bb..2c1e5b0d19019a0546f9988d77cfa8c1054b47b1 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -232,7 +232,7 @@ class TestRunner(FHDLTestCase):
 
         inp = yield from get_cu_inputs(dec2, sim)
 
-        yield from ALUHelpers.set_fast_cia(branch, dec2, inp)
+        yield from ALUHelpers.set_cia(branch, dec2, inp)
         yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
         yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
         yield from ALUHelpers.set_cr_a(branch, dec2, inp)