addeds i2c (twi) interface and also support for inouts

diff --git a/pinmap.txt b/pinmap.txt
index ec38619eb31744f15e0280edbd78e29b24cd6542..a6fe30d303e121ae00ac9bd41cbd26af5b73a0e3 100644 (file)
--- a/pinmap.txt
+++ b/pinmap.txt
@@ -1,5 +1,5 @@
 muxed
 0      uart0_tx        spi0_sclk
 1      uart0_rx        spi0_mosi
-2  spi0_ss     uart0_rx
-3  uart1_tx spi0_miso
+2  twi0_sda    spi0_ss
+3  twi0_scl spi0_miso

diff --git a/src/actual_pinmux.py b/src/actual_pinmux.py
index 1c7928d66a70f6d1e009ebeb6e071cc54971cafd..139df1c2ef160ee074c3d917c15a4ec1575a59f5 100644 (file)
--- a/src/actual_pinmux.py
+++ b/src/actual_pinmux.py
@@ -9,7 +9,9 @@ dictionary={
        "spi_sclk"      :"output",
        "spi_mosi"      :"output",
        "spi_ss"                :"output",
-       "spi_miso"      :"input"
+       "spi_miso"      :"input",
+       "twi_sda"       :"inout",
+       "twi_scl"       :"inout"
 }
        
 
@@ -19,8 +21,8 @@ assign_cell='''cell{0}_out=wrmux{0}=={1}?'''
 # second argument is the mux value. 
 # Third argument is the signal from the pinmap file
 input_wire='''         
-               rule assign_input_for_{2}_on_cell{0}(wrmux{0}=={1});
-                       wr{2}<=cell{0}_in;
+               rule assign_{2}_on_cell{0}(wrmux{0}=={1});
+                       {2}<=cell{0}_in;
                endrule
 '''
 #########################################
@@ -49,8 +51,8 @@ for lineno,line in enumerate(pinmap_file):
                ###### check each cell if "peripheral input/inout" then assign its wire ########
                ## Here we check the direction of each signal in the dictionary. 
                ## We choose to keep the dictionary within the code and not user-input 
-               ## since the interfaces are always standard and cannot change from user-to-user
-               ## plus reduces human-error as well :)
+               ## since the interfaces are always standard and cannot change from user-to-user.
+               ## Plus this also reduces human-error as well :)
                for i in range(0,len(line1)-1):
                        digits = str.maketrans(dict.fromkeys('0123456789'))
                        temp=line1[i+1].translate(digits)
@@ -58,8 +60,12 @@ for lineno,line in enumerate(pinmap_file):
                        if(x==None):
                                print("Error: The signal : "+str(line1[i+1])+" in lineno: "+str(lineno)+"of pinmap.txt is not present in the current dictionary.\nSoln: Either update the dictionary or fix typo.")
                                exit(1)
-                       if(x=="input" or x=="inout"):
-                               pinmux=pinmux+input_wire.format(line1[0],i,line1[i+1])+"\n"
+                       if(x=="input"):
+                               print(line1[i+1]+" "+x)
+                               pinmux=pinmux+input_wire.format(line1[0],i,"wr"+line1[i+1])+"\n"
+                       elif(x=="inout"):
+                               print(line1[i+1]+" "+x)
+                               pinmux=pinmux+input_wire.format(line1[0],i,"wr"+line1[i+1]+"_in")+"\n"
                ################################################################################
 ###########################################
 

diff --git a/src/interface_decl.py b/src/interface_decl.py
index 83d6cba48a6ce03a9f91eba3ed3069eff3522dc8..fa34f4ed2a0c6eaf63f60e7e6d8bc984e51103d5 100644 (file)
--- a/src/interface_decl.py
+++ b/src/interface_decl.py
@@ -31,6 +31,15 @@ spiinterface_decl='''
                (*always_ready,always_enabled*) method Action ss_{0}   (Bit#(1) in);
                (*always_ready,always_enabled*) method Bit#(1) miso_{0};
 '''
+
+twiinterface_decl='''
+               (*always_ready,always_enabled*) method Action sda{0}_out (Bit#(1) in);
+               (*always_ready,always_enabled*) method Action sda{0}_outen (Bit#(1) in);
+               (*always_ready,always_enabled*) method Bit#(1) sda{0}_in;
+               (*always_ready,always_enabled*) method Action scl{0}_out (Bit#(1) in);
+               (*always_ready,always_enabled*) method Action scl{0}_outen (Bit#(1) in);
+               (*always_ready,always_enabled*) method Bit#(1) scl{0}_in;
+'''
 #=======================================#
 
 

diff --git a/src/interface_def.py b/src/interface_def.py
index e491c12c1b4788f7a47905338144f77b38e6a1db..8da88ee6da7d5a8bd18c4ee1ffdea6774a474e54 100644 (file)
--- a/src/interface_def.py
+++ b/src/interface_def.py
@@ -36,6 +36,26 @@ spiinterface_def='''
                endmethod
                method Bit#(1) miso_{0}=wrspi{0}_miso;
 '''
+
+twiinterface_def='''
+
+               method Action sda{0}_out (Bit#(1) in);
+                       wrtwi{0}_sda_out<=in;
+               endmethod
+               method Action sda{0}_outen (Bit#(1) in);
+                       wrtwi{0}_sda_outen<=in;
+               endmethod
+               method sda{0}_in=wrtwi{0}_sda_in;
+
+               method Action scl{0}_out (Bit#(1) in);
+                       wrtwi{0}_scl_out<=in;
+               endmethod
+               method Action scl{0}_outen (Bit#(1) in);
+                       wrtwi{0}_scl_outen<=in;
+               endmethod
+               method scl{0}_in=wrtwi{0}_scl_in;
+               
+'''
 #==============================================#
 
 

diff --git a/src/params.py b/src/params.py
index 971bad8298bd229fde9c630a12bf00ca4c5b95dc..7257f00fa34d1e9743765cf49c8aca72e9441e7f 100644 (file)
--- a/src/params.py
+++ b/src/params.py
@@ -3,6 +3,7 @@ N_MUX=1         # number of selection lines for the mux per io
 N_IO=4
 N_UART=2
 N_SPI=1
+N_TWI=1
 #================#
 
 

diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py
index e4a2176146c4958207b54dc712e28ac97b151ecf..654eb6bcc9e3f9fbdb8d276adbd5bd6219e70d89 100644 (file)
--- a/src/pinmux_generator.py
+++ b/src/pinmux_generator.py
@@ -90,6 +90,11 @@ for i in range(0,N_SPI):
        bsv_file.write('''
                // interface declaration between SPI-{0} and pinmux'''.format(i))
        bsv_file.write(spiinterface_decl.format(i));
+
+for i in range(0,N_TWI):
+       bsv_file.write('''
+               // interface declaration between TWI-{0} and pinmux'''.format(i))
+       bsv_file.write(twiinterface_decl.format(i));
 ################################################################
 
 ####=== finish interface definition and start module definition===####
@@ -121,6 +126,11 @@ for i in range(0,N_SPI):
        bsv_file.write('''\n            // following wires capture the parameters to the IO CELL if spi-{0} is 
                // allotted to it'''.format(i))
        bsv_file.write(spiwires.format(i))
+
+for i in range(0,N_TWI):
+       bsv_file.write('''\n            // following wires capture the parameters to the IO CELL if twi-{0} is 
+               // allotted to it'''.format(i))
+       bsv_file.write(twiwires.format(i))
 bsv_file.write("\n")
 ######################################################################
 #########################== Actual pinmuxing ==#######################
@@ -141,5 +151,7 @@ for i in range(0,N_UART):
        bsv_file.write(uartinterface_def.format(i))
 for i in range(0,N_SPI):
        bsv_file.write(spiinterface_def.format(i))
+for i in range(0,N_TWI):
+       bsv_file.write(twiinterface_def.format(i))
 bsv_file.write(footer)
 ########################################################################

diff --git a/src/wire_def.py b/src/wire_def.py
index d7e3e8a3b8552b34e1a9958e7e0d76c074ea2578..f9d6ce0d7afb7b9083ee0a9b2301cc84df49d5ba 100644 (file)
--- a/src/wire_def.py
+++ b/src/wire_def.py
@@ -35,5 +35,19 @@ spiwires='''
                                                                                                                                drivestrength:0, opendrain_en:0}};
                
 '''
+twiwires='''
+               Wire#(Bit#(1)) wrtwi{0}_sda_out<-mkDWire(0);
+               Wire#(Bit#(1)) wrtwi{0}_sda_outen<-mkDWire(0);
+               Wire#(Bit#(1)) wrtwi{0}_sda_in<-mkDWire(0);
+               Wire#(Bit#(1)) wrtwi{0}_scl_out<-mkDWire(0);
+               Wire#(Bit#(1)) wrtwi{0}_scl_outen<-mkDWire(0);
+               Wire#(Bit#(1)) wrtwi{0}_scl_in<-mkDWire(0);
+               GenericIOType   twi{0}_sda_io = GenericIOType{{outputval:wrtwi{0}_sda_out, output_en:wrtwi{0}_sda_outen, input_en:~wrtwi{0}_sda_outen,
+                                                                                                                                  pullup_en:0, pulldown_en:0, pushpull_en:0,
+                                                                                                                                       drivestrength:0, opendrain_en:0}};
+               GenericIOType   twi{0}_scl_io = GenericIOType{{outputval:wrtwi{0}_scl_out, output_en:wrtwi{0}_scl_outen, input_en:~wrtwi{0}_scl_outen,
+                                                                                                                          pullup_en:0, pulldown_en:0, pushpull_en:0,
+                                                                                                                               drivestrength:0, opendrain_en:0}};
+'''
 #===================================#