correct flexbus connections

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 2fdb7d26132598734801261b14cc4aa12c553843..51902fcf6c126dd46223ee59c22ec524941cadc6 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -200,6 +200,7 @@ else"""
         if stype is None:
             stype = pname
         ret = []
+        ret.append("//%s %s %s %s %s" % (name, ptyp, typ, pname, stype))
         if ptyp == 'fast':
             sname = self.get_iname(count)
             ps = "slow_peripherals.%s" % sname

diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py
index d406a46c247bfdd517d0088f85896d508bdc01ce..726f5be0956cd5d6485a8c09eee8e0c86bbe7607 100644 (file)
--- a/src/bsv/peripheral_gen/flexbus.py
+++ b/src/bsv/peripheral_gen/flexbus.py
@@ -34,6 +34,7 @@ class flexbus(PBase):
     def pinname_out(self, pname):
         return {'ale': 'flexbus_side.m_ALE',
                 'oe': 'flexbus_side.m_OEn',
+                'tbst': 'flexbus_side.m_TBSTn',
                 'rw': 'flexbus_side.m_R_Wn',
                 }.get(pname, '')
 
@@ -42,7 +43,6 @@ class flexbus(PBase):
         for pname, sz, ptype in [
             ('cs', 6, 'out'),
             ('bwe', 4, 'out'),
-            ('tbst', 2, 'out'),
             ('tsiz', 2, 'out'),
             ('ad_out', 32, 'out'),
             ('ad_in', 32, 'in'),
@@ -59,7 +59,6 @@ class flexbus(PBase):
         for pname, stype, ptype in [
             ('cs', 'm_FBCSn', 'out'),
             ('bwe', 'm_BWEn', 'out'),
-            ('tbst', 'm_TBSTn', 'out'),
             ('tsiz', 'm_TSIZ', 'out'),
             ('ad_out', 'm_AD', 'out'),
             ('ad_in', 'm_din', 'in'),