radeonsi: fix the top-of-pipe fence on SI

SI doesn't have MEM.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c
index be394119af631a52a8f000e72ff77e6010038f0c..46d0289c90b1894f13fccb8127713a339af5c9fc 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -266,7 +266,8 @@ static void si_fine_fence_set(struct si_context *ctx,
        if (flags & PIPE_FLUSH_TOP_OF_PIPE) {
                struct radeon_cmdbuf *cs = ctx->gfx_cs;
                radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-               radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
+               radeon_emit(cs, S_370_DST_SEL(ctx->chip_class >= CIK ? V_370_MEM
+                                                                    : V_370_MEM_GRBM) |
                        S_370_WR_CONFIRM(1) |
                        S_370_ENGINE_SEL(V_370_PFP));
                radeon_emit(cs, fence_va);