remove DAR from PortInterface (where is the data going? there is no place

to put DAR if transmitted over PortInterface? what receives it? nothing

diff --git a/src/soc/config/test/test_pi2ls.py b/src/soc/config/test/test_pi2ls.py
index c3545af1fe6b26a46a980145b412753bfe3030bd..31b92363c2ca3ce897f376f8bdc6c57383bf29fc 100644 (file)
--- a/src/soc/config/test/test_pi2ls.py
+++ b/src/soc/config/test/test_pi2ls.py
@@ -62,27 +62,25 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
     # XXX TODO: wait_addr should check for exception
     exc_info = yield from get_exception_info(port1.exc_o)
     exc_happened = exc_info.happened
-    dar_o = yield port1.dar_o
     if exc_happened:
         print("print fast ST exception happened")
         yield # MUST wait for one clock cycle before de-asserting these
         yield port1.is_st_i.eq(0)  # end
         yield port1.addr.ok.eq(0)  # set !ok
         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
-        return "fast", exc_info, dar_o
+        return "fast", exc_info
 
     yield from wait_addr(port1)             # wait until addr ok
 
     exc_info = yield from get_exception_info(port1.exc_o)
     exc_happened = exc_info.happened
-    dar_o = yield port1.dar_o
     if exc_happened:
         print("print fast ST exception happened")
         yield # MUST wait for one clock cycle before de-asserting these
         yield port1.is_st_i.eq(0)  # end
         yield port1.addr.ok.eq(0)  # set !ok
         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
-        return "fast", exc_info, dar_o
+        return "fast", exc_info
 
 
     # yield # not needed, just for checking
@@ -93,7 +91,6 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
     yield
     yield port1.st.ok.eq(0)
     exc_info = yield from get_exception_info(port1.exc_o)
-    dar_o = yield port1.dar_o
     exc_happened = exc_info.happened
     if exc_happened:
         print("print fast ST exception happened")
@@ -101,11 +98,10 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
         yield port1.is_st_i.eq(0)  # end
         yield port1.addr.ok.eq(0)  # set !ok
         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
-        return "fast", exc_info, dar_o
+        return "fast", exc_info
 
     yield from wait_busy(port1,debug="pi_st_E") # wait while busy
     exc_info = yield from get_exception_info(port1.exc_o)
-    dar_o = yield port1.dar_o
     exc_happened = exc_info.happened
     if exc_happened:
         yield  # needed if mmu/dache is used
@@ -113,7 +109,7 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
         yield port1.addr.ok.eq(0)  # set !ok
         yield port1.is_dcbz_i.eq(0)  # reset dcbz too
         yield  # needed if mmu/dache is used
-        return "slow", exc_info, dar_o
+        return "slow", exc_info
 
     # can go straight to reset.
     yield port1.is_st_i.eq(0)  # end
@@ -121,7 +117,7 @@ def pi_st(port1, addr, data, datalen, msr_pr=0, is_dcbz=0):
     yield port1.is_dcbz_i.eq(0)  # reset dcbz too
     yield  # needed if mmu/dache is used
 
-    return None, None, None
+    return None, None
 
 def get_exception_info(exc_o):
     attrs = []
@@ -149,20 +145,18 @@ def pi_ld(port1, addr, datalen, msr_pr=0):
     yield Settle()
     yield from wait_addr(port1)             # wait until addr ok
     exc_info = yield from get_exception_info(port1.exc_o)
-    dar_o = yield port1.dar_o
     exc_happened = exc_info.happened
     if exc_happened:
         print("print fast LD exception happened")
         yield # MUST wait for one clock cycle before de-asserting these
         yield port1.is_ld_i.eq(0)  # end
         yield port1.addr.ok.eq(0)  # set !ok
-        return None, "fast", exc_info, dar_o
+        return None, "fast", exc_info
 
     yield
     yield from wait_ldok(port1)             # wait until ld ok
     data = yield port1.ld.data
     exc_info = yield from get_exception_info(port1.exc_o)
-    dar_o = yield port1.dar_o
     exc_happened = yield port1.exc_o.happened
     exc_happened = exc_info.happened
 
@@ -170,17 +164,16 @@ def pi_ld(port1, addr, datalen, msr_pr=0):
     yield port1.is_ld_i.eq(0)  # end
     yield port1.addr.ok.eq(0)  # set !ok
     if exc_happened:
-        return None, "slow", exc_info, dar_o
+        return None, "slow", exc_info
 
     yield from wait_busy(port1, debug="pi_ld_E") # wait while busy
 
     exc_info = yield from get_exception_info(port1.exc_o)
-    dar_o = yield port1.dar_o
     exc_happened = exc_info.happened
     if exc_happened:
-        return None, "slow", exc_info, dar_o
+        return None, "slow", exc_info
 
-    return data, None, None, None
+    return data, None, None
 
 
 def pi_ldst(arg, dut, msr_pr=0):

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index d4e7b60c9b7356db71da53679db0a6e346aea360..03be6bcab3800f48221e91b2ad3096c0360e768d 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -110,7 +110,6 @@ class PortInterface(RecordObject):
         # addr is valid (TLB, L1 etc.)
         self.addr_ok_o = Signal(reset_less=True)
         self.exc_o = LDSTException("exc")
-        self.dar_o = Signal(64, reset_less=True)
 
         # LD/ST
         self.ld = Data(regwid, "ld_data_o")  # ok to be set by L0 Cache/Buf
@@ -145,7 +144,6 @@ class PortInterface(RecordObject):
                 inport.busy_o.eq(self.busy_o),
                 inport.addr_ok_o.eq(self.addr_ok_o),
                 inport.exc_o.eq(self.exc_o),
-                inport.dar_o.eq(self.dar_o),
                 inport.mmu_done.eq(self.mmu_done),
                 inport.ldst_error.eq(self.ldst_error),
                 inport.cache_paradox.eq(self.cache_paradox)

diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index d5ceb6077f352f5445af3aae59c7935b03653f5d..259382827482beed56072b046e89b4e9f5c03082 100644 (file)
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -113,7 +113,7 @@ def _test_loadstore1_invalid(dut, mem):
     print("=== test invalid ===")
 
     addr = 0
-    ld_data, exctype, exc, _ = yield from pi_ld(pi, addr, 8, msr_pr=1)
+    ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
     print("ld_data", ld_data, exctype, exc)
     assert (exctype == "slow")
     invalid = exc.invalid
@@ -141,11 +141,11 @@ def _test_loadstore1(dut, mem):
         yield from pi_st(pi, addr, data, 8, msr_pr=1)
         yield
 
-        ld_data, exctype, exc, _ = yield from pi_ld(pi, addr, 8, msr_pr=1)
+        ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
         assert ld_data == 0xf553b658ba7e1f51
         assert exctype is None
 
-        ld_data, exctype, exc, _  = yield from pi_ld(pi, addr, 8, msr_pr=1)
+        ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
         assert ld_data == 0xf553b658ba7e1f51
         assert exctype is None
 
@@ -154,7 +154,7 @@ def _test_loadstore1(dut, mem):
         print("done_dcbz ===============")
         yield
 
-        ld_data, exctype, exc, _  = yield from pi_ld(pi, addr, 8, msr_pr=1)
+        ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
         print("ld_data after dcbz")
         print(ld_data)
         assert ld_data == 0
@@ -163,7 +163,7 @@ def _test_loadstore1(dut, mem):
     if test_exceptions:
         print("=== alignment error (ld) ===")
         addr = 0xFF100e0FF
-        ld_data, exctype, exc, _ = yield from pi_ld(pi, addr, 8, msr_pr=1)
+        ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
         if exc:
             alignment = exc.alignment
             happened = exc.happened
@@ -190,7 +190,7 @@ def _test_loadstore1(dut, mem):
 
         print("=== alignment error (st) ===")
         addr = 0xFF100e0FF
-        exctype, exc, _ = yield from pi_st(pi, addr,0, 8, msr_pr=1)
+        exctype, exc = yield from pi_st(pi, addr,0, 8, msr_pr=1)
         if exc:
             alignment = exc.alignment
             happened = exc.happened
@@ -209,7 +209,7 @@ def _test_loadstore1(dut, mem):
     if True:
         print("=== no alignment error (ld) ===")
         addr = 0x100e0
-        ld_data, exctype, exc, _ = yield from pi_ld(pi, addr, 8, msr_pr=1)
+        ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
         print("ld_data", ld_data, exctype, exc)
         if exc:
             alignment = exc.alignment
@@ -226,8 +226,7 @@ def _test_loadstore1(dut, mem):
 
         for addr in addrs:
             print("== RANDOM addr ==",hex(addr))
-            ld_data, exctype, exc, _  = \
-                                yield from pi_ld(pi, addr, 8, msr_pr=1)
+            ld_data, exctype, exc  = yield from pi_ld(pi, addr, 8, msr_pr=1)
             print("ld_data[RANDOM]",ld_data,exc,addr)
             assert (exctype == None)
 
@@ -239,8 +238,7 @@ def _test_loadstore1(dut, mem):
         # readback written data and compare
         for addr in addrs:
             print("== RANDOM addr ==",hex(addr))
-            ld_data, exctype, exc, _ = \
-                                yield from pi_ld(pi, addr, 8, msr_pr=1)
+            ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr_pr=1)
             print("ld_data[RANDOM_READBACK]",ld_data,exc,addr)
             assert (exctype == None)
             assert (ld_data == 0xFF*addr)