add DEC SPR to CoreState and PowerDecoder, activate 0x900 interrupt

diff --git a/src/soc/config/state.py b/src/soc/config/state.py
index e4cef69cf85dedbf6d2c9b7a3b5ea2ceecfde0d3..3fc919671fe984800d6da46c60170d19dfa8d266 100644 (file)
--- a/src/soc/config/state.py
+++ b/src/soc/config/state.py
@@ -8,3 +8,4 @@ class CoreState(RecordObject):
         self.pc = Signal(64)      # Program Counter (CIA, NIA)
         self.msr = Signal(64)     # Machine Status Register (MSR)
         self.eint = Signal()      # External Interrupt
+        self.dec = Signal(64)     # DEC SPR (again, for interrupt generation)

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 505fce3d6fca2567545384e56183a8fa0fc35ce9..f7e55f1a11fe3ec9596b77abaaea2217ef7533a4 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -142,6 +142,7 @@ class TT:
     TRAP = 1<<2
     ADDR = 1<<3
     EINT = 1<<4  # external interrupt
-    ILLEG = 1<<5 # currently the max, therefore traptype must be 5 bits
+    DEC = 1<<5   # decrement counter
+    ILLEG = 1<<6 # currently the max, therefore traptype must be 5 bits
     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
-    size = 6 # MUST update this to contain the full number of Trap Types
+    size = 7 # MUST update this to contain the full number of Trap Types

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index f6b88a8510f92a7f5d5e82f021ca84c5d909c38f..83238391b1b666fcf273a17e11bd025267f65b86 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -633,8 +633,9 @@ class PowerDecode2(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        state = self.state
         e_out, op, do_out = self.e, self.dec.op, self.e.do
-        msr, cia, ext_irq = self.state.msr, self.state.pc, self.state.eint
+        dec_spr, msr, cia, ext_irq = state.dec, state.msr, state.pc, state.eint
 
         # fill in for a normal instruction (not an exception)
         # copy over if non-exception, non-privileged etc. is detected
@@ -756,6 +757,10 @@ class PowerDecode2(Elaboratable):
         with m.If(ext_irq & msr[MSR.EE]):
             self.trap(m, TT.EINT, 0x500)
 
+        # decrement counter: TODO 32-bit version (MSR.LPCR)
+        with m.If(dec_spr[63] & msr[MSR.EE]): # v3.0B 6.5.11 p1076
+            self.trap(m, TT.DEC, 0x900)   # v3.0B 6.5 p1065
+
         # privileged instruction trap
         with m.Elif(is_priv_insn & msr[MSR.PR]):
             self.trap(m, TT.PRIV, 0x700)