make FU-FU DepCell a row

diff --git a/setup.py b/setup.py
index 5bb9b92ea8b60b9e5a571d13ad5b6c07eca38e4b..4f4f03381c809ab29354c14ada606ffb02e0ae9a 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -9,7 +9,7 @@ NEWS = open(os.path.join(here, 'NEWS.txt')).read()
 version = '0.0.1'
 
 install_requires = [
-    'sfpy',
+#    'sfpy',
     'ieee754fpu',
 ]
 

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index a631a6524b96b0a3634ea78f5dca4fbeaf4e3741..9e97a7476628cf02e6a53114ba424ecdd1f012c8 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -7,19 +7,20 @@ from nmutil.latch import SRLatch
 class DepCell(Elaboratable):
     """ FU Dependency Cell
     """
-    def __init__(self):
+    def __init__(self, llen=1):
+        self.llen = llen
         # inputs
-        self.pend_i = Signal(reset_less=True)    # pending bit in (left)
-        self.issue_i = Signal(reset_less=True)   # Issue in (top)
-        self.go_i = Signal(reset_less=True)      # Go read/write in (left)
-        self.die_i = Signal(reset_less=True)     # Go die in (left)
+        self.pend_i = Signal(llen, reset_less=True)    # pending bit in (left)
+        self.issue_i = Signal(llen, reset_less=True)   # Issue in (top)
+        self.go_i = Signal(llen, reset_less=True)      # Go read/write in (left)
+        self.die_i = Signal(llen, reset_less=True)     # Go die in (left)
 
         # wait
-        self.wait_o = Signal(reset_less=True)  # wait out (right)
+        self.wait_o = Signal(llen, reset_less=True)  # wait out (right)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.l = l = SRLatch(sync=False) # async latch
+        m.submodules.l = l = SRLatch(sync=False, llen=self.llen) # async latch
 
         # reset on go HI, set on dest and issue
         m.d.comb += l.s.eq(self.issue_i & self.pend_i)
@@ -44,24 +45,25 @@ class DepCell(Elaboratable):
 class FUDependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
-    def __init__(self):
+    def __init__(self, n_fu=1):
+        self.n_fu = n_fu
         # inputs
-        self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
-        self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
-        self.issue_i = Signal(reset_less=True)    # Issue in (top)
+        self.rd_pend_i = Signal(n_fu, reset_less=True) # read pend in (left)
+        self.wr_pend_i = Signal(n_fu, reset_less=True) # write pend in (left)
+        self.issue_i = Signal(n_fu, reset_less=True)    # Issue in (top)
 
-        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
-        self.go_die_i = Signal(reset_less=True) # Go Die in (left)
+        self.go_wr_i = Signal(n_fu, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu, reset_less=True)  # Go Read in (left)
+        self.go_die_i = Signal(n_fu, reset_less=True) # Go Die in (left)
 
         # outputs (latched rd/wr wait)
-        self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
-        self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
+        self.rd_wait_o = Signal(n_fu, reset_less=True) # read wait out (right)
+        self.wr_wait_o = Signal(n_fu, reset_less=True) # write wait out (right)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_c = rd_c = DepCell()
-        m.submodules.wr_c = wr_c = DepCell()
+        m.submodules.rd_c = rd_c = DepCell(self.n_fu)
+        m.submodules.wr_c = wr_c = DepCell(self.n_fu)
 
         # connect issue
         for c in [rd_c, wr_c]:

diff --git a/src/scoreboard/fu_fu_matrix.py b/src/scoreboard/fu_fu_matrix.py
index 5d8b2cb21d7db509fd6633b9f8b6cfcfc1c52aad..ee715bdbf292d92495d4dac653aa1f80292b6fcc 100644 (file)
--- a/src/scoreboard/fu_fu_matrix.py
+++ b/src/scoreboard/fu_fu_matrix.py
@@ -37,11 +37,10 @@ class FUFUDepMatrix(Elaboratable):
         # ---
         # matrix of dependency cells
         # ---
-        dm = Array(Array(FUDependenceCell() for r in range(self.n_fu_row)) \
+        dm = Array(FUDependenceCell(self.n_fu_row) \
                                             for f in range(self.n_fu_col))
         for x in range(self.n_fu_col):
-            for y in range(self.n_fu_row):
-                setattr(m.submodules, "dm_fx%d_fy%d" % (x, y), dm[x][y])
+                setattr(m.submodules, "dm%d" % x, dm[x])
 
         # ---
         # array of Function Unit Readable/Writable: row-length, horizontal
@@ -73,23 +72,24 @@ class FUFUDepMatrix(Elaboratable):
             rd_wait_o = []
             wr_wait_o = []
             for x in range(self.n_fu_col):
-                dc = dm[x][y]
+                dc = dm[x]
                 # accumulate cell outputs rd/wr-pending
-                rd_wait_o.append(dc.rd_wait_o)
-                wr_wait_o.append(dc.wr_wait_o)
+                rd_wait_o.append(dc.rd_wait_o[y])
+                wr_wait_o.append(dc.wr_wait_o[y])
             # connect cell reg-select outputs to Reg Vector In
             m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
                          fu.wr_pend_i.eq(Cat(*wr_wait_o)),
                         ]
+
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
         # ---
         for x in range(self.n_fu_col):
+            dc = dm[x]
             issue_i = []
             for y in range(self.n_fu_row):
-                dc = dm[x][y]
                 # accumulate cell inputs issue
-                issue_i.append(dc.issue_i)
+                issue_i.append(dc.issue_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += Cat(*issue_i).eq(self.issue_i)
 
@@ -101,17 +101,18 @@ class FUFUDepMatrix(Elaboratable):
             go_wr_i = []
             go_die_i = []
             for x in range(self.n_fu_col):
-                dc = dm[x][y]
+                dc = dm[x]
                 # accumulate cell go_rd/go_wr
-                go_rd_i.append(dc.go_rd_i)
-                go_wr_i.append(dc.go_wr_i)
-                go_die_i.append(dc.go_die_i)
+                go_rd_i.append(dc.go_rd_i[y])
+                go_wr_i.append(dc.go_wr_i[y])
+                go_die_i.append(dc.go_die_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
                          Cat(*go_wr_i).eq(self.go_wr_i),
                          Cat(*go_die_i).eq(self.go_die_i),
                         ]
 
+
         # ---
         # connect Matrix pending
         # ---
@@ -119,16 +120,16 @@ class FUFUDepMatrix(Elaboratable):
             rd_pend_i = []
             wr_pend_i = []
             for x in range(self.n_fu_col):
+                dc = dm[x]
                 if x == y: # ignore hazards on the diagonal: self-against-self
                     dummyrd = Signal(reset_less=True)
                     dummywr = Signal(reset_less=True)
                     rd_pend_i.append(dummyrd)
                     wr_pend_i.append(dummywr)
                     continue
-                dc = dm[x][y]
                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
-                rd_pend_i.append(dc.rd_pend_i)
-                wr_pend_i.append(dc.wr_pend_i)
+                rd_pend_i.append(dc.rd_pend_i[y])
+                wr_pend_i.append(dc.wr_pend_i[y])
             # wire up inputs from module to row cell inputs (Cat is gooood)
             m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
                          Cat(*wr_pend_i).eq(self.wr_pend_i),