add QSPI support to arty_a7

diff --git a/src/ls2.py b/src/ls2.py
index b3b9e62a525e0d151279795761f9915ca04355e3..8cedbacf76754b7d17caca202c5dfa5e3a30159d 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -681,7 +681,8 @@ def build_platform(fpga, firmware):
     if platform is not None and \
        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
         # Override here to get FlashResource out of the way and enable Tercel
-        # direct access to the SPI flash
+        # direct access to the SPI flash.
+        # each pin needs a separate direction control
         spi_0_ios = [
             Resource("spi_0", 0,
                      Subsignal("dq0",   Pins("W2", dir="io")),
@@ -697,6 +698,22 @@ def build_platform(fpga, firmware):
                                                        "dq2":1, "dq3": 1,
                                                        "cs_n":0})
 
+    if platform is not None and \
+       fpga in ['arty_a7']:
+        # each pin needs a separate direction control
+        spi_0_ios = [
+            Resource("spi_0", 0,
+                     Subsignal("dq0",  Pins("K17", dir="io")),
+                     Subsignal("dq1",  Pins("K18", dir="io")),
+                     Subsignal("dq2",  Pins("L14", dir="io")),
+                     Subsignal("dq3",  Pins("M14", dir="io")),
+                     Subsignal("cs_n", Pins("L13", dir="o")),
+                     Subsignal("clk",  Pins("L16", dir="o")),
+                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+        ]
+        platform.add_resources(spi_0_ios)
+        spi_0_pins = platform.request("spi_0", 0)
+
     print ("spiflash pins", spi_0_pins)
 
     # Get Ethernet RMII resource pins