invert reset and chip-select on dram, and initialise uart input

in iverilog sim

diff --git a/src/simsoctb.v b/src/simsoctb.v
index f51ed07d9c4cd5eec849b4f3fd7bfe0627125d7e..3ba4c910b50f012984f6b549f39de6acd58065b0 100644 (file)
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -47,11 +47,11 @@ module simsoctb;
   ddr3 #(
     .check_strict_timing(0)
   ) ram_chip (
-    .rst_n(dram_rst),
+    .rst_n(~dram_rst),
     .ck(dram_ck),
     .ck_n(~dram_ck),
     .cke(dram_cke),
-    .cs_n(dram_cs_n),
+    .cs_n(~dram_cs_n),
     .ras_n(dram_ras_n),
     .cas_n(dram_cas_n),
     .we_n(dram_we_n),
@@ -69,7 +69,7 @@ module simsoctb;
 
   // uart, LEDs, switches
   wire uart_tx ;
-  wire uart_rx;
+  reg uart_rx = 0;
   wire led_0;
   wire led_1;
   wire led_2;