add assertion checking bus write against memory write port granularity

diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py
index 630b53c090bbd0ffe5141c72bfef2e56558da4a9..c518ff9a718bea68f334b853783936b761d7b273 100644 (file)
--- a/nmigen_soc/wishbone/sram.py
+++ b/nmigen_soc/wishbone/sram.py
@@ -86,7 +86,11 @@ class SRAM(Elaboratable):
                 wrport.addr.eq(self.bus.adr[:len(rdport.addr)]),
                 wrport.data.eq(self.bus.dat_w)
             ]
-            for i in range(4):
+            n_wrport = wrport.en.shape()[0]
+            n_bussel = self.bus.sel.shape()[0]
+            assert n_wrport == n_bussel, "bus enable count %d " \
+                    "must match memory wen count %d" % (n_wrport, n_bussel)
+            for i in range(n_wrport):
                 m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb &
                                             self.bus.we & self.bus.sel[i])