sigh gramWishbone is not WB4-pipeline-burst-compliant

compensate for this with the "usual" WB3 classic trick stall=cyc&~ack;

diff --git a/Makefile b/Makefile
index 0943765607783c868a7d6430a1a61bfbc1369478..a41fe72aae852011623794b808f4db85d6332e5c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -26,7 +26,7 @@ endif
 
 # Hello world
 MEMORY_SIZE=8192
-RAM_INIT_FILE=hello_world/hello_world.bin
+#RAM_INIT_FILE=hello_world/hello_world.bin
 RAM_INIT_FILE=coldboot/coldboot.bin
 SIM_MAIN_BRAM=false
 
@@ -44,8 +44,8 @@ FPGA_TARGET ?= verilator
 
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true
-CLK_INPUT=50000000
-CLK_FREQUENCY=50000000
+CLK_INPUT=100000000
+CLK_FREQUENCY=100000000
 clkgen=fpga/clk_gen_bypass.vhd
 endif
 

diff --git a/coldboot/Makefile b/coldboot/Makefile
index 7ac6333302f51364e88ef99074e6cc6acf9df639..1180178e7746f40420697d18e20179148876c391 100644 (file)
--- a/coldboot/Makefile
+++ b/coldboot/Makefile
@@ -7,8 +7,8 @@ endif
 
 # a multiplier factor on sleep loops. this allows simulations to run
 # at much shorter intervals
-LONG_TIMER_MULT ?= 100000
-SHORT_TIMER_MULT ?= 1000
+LONG_TIMER_MULT ?= 10000
+SHORT_TIMER_MULT ?= 100
 #LONG_TIMER_MULT ?= 1
 #SHORT_TIMER_MULT ?= 1
 

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index d85ae7682260037ed20be709d4a4644264f687c4..408b90ce0e45344b0ec4bf3c9f35e4bf6e7ede17 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -59,12 +59,12 @@ void isr(void) {
 }
 
 int main(void) {
-       const int kNumIterations = 65536;
+       const int kNumIterations = 14;
        int res, failcnt = 0;
        uint32_t tmp;
        volatile uint32_t *ram = DRAM_BASE;
        console_init();
-       puts("Firmware launched...\n");
+       //puts("Firmware launched...\n");
 
        puts("DRAM init... ");
        struct gramCtx ctx;
@@ -72,8 +72,8 @@ int main(void) {
                .mode_registers = {
                        0x320, 0x6, 0x200, 0x0
                },
-               .rdly_p0 = 2,
-               .rdly_p1 = 2,
+               .rdly_p0 = 0,
+               .rdly_p1 = 0,
        };
        struct gramProfile profile2;
        gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000,
@@ -81,15 +81,25 @@ int main(void) {
                               (void*)DRAM_INIT_BASE); //0x00008000);
        puts("done\n");
 
+#if 0
+    // quick write/read
+    writel(0xDEAF0000, (unsigned long)&(ram[0]));
+    tmp = readl((unsigned long)&(ram[0]));
+       puts("read ");
+       uart_writeuint32(tmp);
+
+    return 0;
+#endif
+
+#if 0
        puts("Rdly\np0: ");
        for (size_t i = 0; i < 8; i++) {
                profile2.rdly_p0 = i;
                gram_load_calibration(&ctx, &profile2);
-        puts("loaded ");
                gram_reset_burstdet(&ctx);
-        puts("burstreset ");
+
                for (size_t j = 0; j < 128; j++) {
-                       tmp = readl((unsigned long)&ram[i]);
+                       tmp = readl((unsigned long)&(ram[i]));
                }
                if (gram_read_burstdet(&ctx, 0)) {
                        puts("1");
@@ -103,11 +113,9 @@ int main(void) {
        for (size_t i = 0; i < 8; i++) {
                profile2.rdly_p1 = i;
                gram_load_calibration(&ctx, &profile2);
-        puts("loaded ");
                gram_reset_burstdet(&ctx);
-        puts("burstreset ");
                for (size_t j = 0; j < 128; j++) {
-                       tmp = readl((unsigned long)&ram[i]);
+                       tmp = readl((unsigned long)&(ram[i]));
                }
                if (gram_read_burstdet(&ctx, 1)) {
                        puts("1");
@@ -127,6 +135,8 @@ int main(void) {
        }
        puts("done\n");
 
+#endif
+
        puts("Auto calibration profile:");
        puts("p0 rdly:");
        uart_writeuint32(profile2.rdly_p0);
@@ -136,16 +146,16 @@ int main(void) {
 
        puts("DRAM test... \n");
        for (size_t i = 0; i < kNumIterations; i++) {
-               ram[i] = 0xDEAF0000 | i*4;
+               writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
        }
 
        for (size_t i = 0; i < kNumIterations; i++) {
-               if (ram[i] != (0xDEAF0000 | i*4)) {
+               if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
                        puts("fail : *(0x");
                        uart_writeuint32(&ram[i]);
                        puts(") = ");
                        uart_writeuint32(ram[i]);
-                       putchar('\n');
+                       puts("\n");
                        failcnt++;
 
                        if (failcnt > 10) {
@@ -156,8 +166,6 @@ int main(void) {
        }
        puts("done\n");
 
-       while (1);
-
        return 0;
 }
 

diff --git a/coldboot/powerpc.lds b/coldboot/powerpc.lds
index 99611ab41cea7a6ffc10153e49abb329675ddee0..00aba334ad0e2dc72cef9299a74f9f6288b7dc6e 100644 (file)
--- a/coldboot/powerpc.lds
+++ b/coldboot/powerpc.lds
@@ -7,9 +7,9 @@ SECTIONS
        }
        . = ALIGN(0x1000);
        .text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
-       . = ALIGN(0x1000);
+       . = ALIGN(0x10);
        .data : { *(.data) *(.data.*) *(.got) *(.toc) }
-       . = ALIGN(0x80);
+       . = ALIGN(0x10);
        __bss_start = .;
        .bss : {
                *(.dynsbss)
@@ -20,8 +20,8 @@ SECTIONS
                *(.common)
                *(.bss.*)
        }
-       . = ALIGN(0x80);
+       . = ALIGN(0x10);
        __bss_end = .;
-       . = . + 0x4000;
+       . = . + 0x5000;
        __stack_top = .;
 }

diff --git a/lib/console.c b/lib/console.c
index b44c024f5251b31e2d8ffbfb91856a2337f66d6f..d5c8af1e38af036c554b4e9a5bb8673d3dba5c1d 100644 (file)
--- a/lib/console.c
+++ b/lib/console.c
@@ -155,6 +155,7 @@ int getchar(void)
 
 int putchar(int c)
 {
+    return c;
        if (uart_is_std) {
                while(std_uart_tx_full())
                        /* Do Nothing */;

diff --git a/libgram/src/calibration.c b/libgram/src/calibration.c
index 21e698c6312e34da1d2f25533f186a2cec41e2d4..8626b62542039efa42675f1fd2c79d3b76c21cff 100644 (file)
--- a/libgram/src/calibration.c
+++ b/libgram/src/calibration.c
@@ -58,13 +58,13 @@ int gram_generate_calibration(const struct gramCtx *ctx, struct gramProfile *pro
                profile->rdly_p0 = rdly;
                gram_load_calibration(ctx, profile);
                gram_reset_burstdet(ctx);
-        puts("reset burst");
+        //puts("reset burst");
 
                for (i = 0; i < 128; i++) {
-                       tmp = readl(&ram[i]);
+                       tmp = readl((unsigned long)&(ram[i]));
                }
 
-        puts("read burst?");
+        //puts("read burst?");
                if (gram_read_burstdet(ctx, 0)) {
                        min_rdly_p0 = rdly;
                        break;
@@ -97,7 +97,7 @@ int gram_generate_calibration(const struct gramCtx *ctx, struct gramProfile *pro
                gram_reset_burstdet(ctx);
 
                for (i = 0; i < 128; i++) {
-                       tmp = readl(&ram[i]);
+                       tmp = readl((unsigned long)&(ram[i]));
                }
 
                if (!gram_read_burstdet(ctx, 0)) {
@@ -114,7 +114,7 @@ int gram_generate_calibration(const struct gramCtx *ctx, struct gramProfile *pro
                gram_reset_burstdet(ctx);
 
                for (i = 0; i < 128; i++) {
-                       tmp = readl(&ram[i]);
+                       tmp = readl((unsigned long)&(ram[i]));
                }
 
                if (!gram_read_burstdet(ctx, 1)) {
@@ -136,10 +136,7 @@ int gram_generate_calibration(const struct gramCtx *ctx, struct gramProfile *pro
 
 void gram_load_calibration(const struct gramCtx *ctx, const struct gramProfile *profile) {
        dfii_setsw(ctx, true);
-    puts("set rdly 0?");
        set_rdly(ctx, 0, profile->rdly_p0);
-    puts("set rdly 1?");
        set_rdly(ctx, 1, profile->rdly_p1);
-    puts("set hw");
        dfii_setsw(ctx, false);
 }

diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c
index 7fbf9278cf6bc753737fa85d62d4fdeecb678cac..a915a274b4d32fc051651260d5ca41fa1fd42621 100644 (file)
--- a/libgram/src/dfii.c
+++ b/libgram/src/dfii.c
@@ -14,6 +14,10 @@ static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) {
 #endif
 }
 
+void dfii_rst(const struct gramCtx *ctx) {
+               dfii_setcontrol(ctx, DFII_CONTROL_ODT| DFII_CONTROL_RESET);
+}
+
 void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
        if (software_control) {
                dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|
@@ -27,7 +31,7 @@ void dfii_set_p0_address(const struct gramCtx *ctx, uint32_t val) {
 #ifdef GRAM_RW_FUNC
        gram_write(ctx, (void*)&(ctx->core->phases[0].address), val);
 #else
-       writel(val, (unsigned long)&ctx->core->phases[0].address);
+       writel(val, (unsigned long)&(ctx->core->phases[0].address));
 #endif
 }
 
@@ -35,7 +39,7 @@ void dfii_set_p0_baddress(const struct gramCtx *ctx, uint32_t val) {
 #ifdef GRAM_RW_FUNC
        gram_write(ctx, (void*)&(ctx->core->phases[0].baddress), val);
 #else
-       writel(val, (unsigned long)&ctx->core->phases[0].baddress);
+       writel(val, (unsigned long)&(ctx->core->phases[0].baddress));
 #endif
 }
 
@@ -44,8 +48,8 @@ void dfii_p0_command(const struct gramCtx *ctx, uint32_t cmd) {
        gram_write(ctx, (void*)&(ctx->core->phases[0].command), cmd);
        gram_write(ctx, (void*)&(ctx->core->phases[0].command_issue), 1);
 #else
-       writel(cmd, (unsigned long)&ctx->core->phases[0].command);
-       writel(1, (unsigned long)&ctx->core->phases[0].command_issue);
+       writel(cmd, (unsigned long)&(ctx->core->phases[0].command));
+       writel(1, (unsigned long)&(ctx->core->phases[0].command_issue));
 #endif
 }
 
@@ -61,13 +65,13 @@ void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile)
        /* Release reset */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);
-       dfii_setcontrol(ctx, DFII_CONTROL_ODT);
+       dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
        cdelay(5*LONG_TIMER_MULT);
 
        /* Bring CKE high */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);
-       dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT);
+       dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
        cdelay(1*LONG_TIMER_MULT);
 
        /* Load Mode Register 2, CWL=5 */

diff --git a/libgram/src/dfii.h b/libgram/src/dfii.h
index 3e84f8c9957cd8013104d44c9cdf67b90a94a56b..8e23b6ddb50f333017ac730561caa2e4ff5a3752 100644 (file)
--- a/libgram/src/dfii.h
+++ b/libgram/src/dfii.h
@@ -14,6 +14,7 @@
 #define DFII_COMMAND_RAS (1 << 3)
 #define DFII_COMMAND_WRDATA (1 << 4)
 
+void dfii_reset(const struct gramCtx *ctx);
 void dfii_setsw(const struct gramCtx *ctx, bool software_control);
 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile);
 void dfii_set_p0_address(const struct gramCtx *ctx, uint32_t val);

diff --git a/libgram/src/init.c b/libgram/src/init.c
index 3d6c7a4eb010b720e1ad06a8e72f529face05a65..91d3fd2493f331bd0d6e2d81d5024f5e77bb8235 100644 (file)
--- a/libgram/src/init.c
+++ b/libgram/src/init.c
@@ -1,19 +1,28 @@
 #include <gram.h>
 #include "dfii.h"
 #include "console.h"
+#include "hw_regs.h"
+#include "helpers.h"
+
+extern void uart_writeuint32(uint32_t val);
 
 int gram_init(struct gramCtx *ctx, const struct gramProfile *profile, void *ddr_base, void *core_base, void *phy_base) {
        ctx->ddr_base = ddr_base;
        ctx->core = core_base;
        ctx->phy = phy_base;
 
+    //puts("phy base");
+    //uart_writeuint32((unsigned long)&(ctx->phy));
+    //puts("bdet");
+    //uart_writeuint32((unsigned long)&(ctx->phy->burstdet));
+
+       //dfii_reset(ctx);
+    //puts("reset\n");
        dfii_setsw(ctx, true);
-    puts("dfii_setsw\n");
+    //puts("dfii_setsw\n");
        dfii_initseq(ctx, profile);
     puts("initseq\n");
        gram_load_calibration(ctx, profile);
-    puts("cal");
-       dfii_setsw(ctx, false);
 
     return GRAM_ERR_NONE;
 }

diff --git a/src/ls2.py b/src/ls2.py
index f45bb97ace257e448705a78091a1a66deb479db6..bcb4b3b39c13fd401ba48a80c3edba7fce169efb 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -234,7 +234,7 @@ class DDR3SoC(SoC, Elaboratable):
         #      ibus  dbus
         #       |     |
         #       +--+--+
-        #          | 
+        #          |
         #      64to32DownCvt
         #          |
         #       arbiter
@@ -358,8 +358,8 @@ class DDR3SoC(SoC, Elaboratable):
                 self.dramcore = drs(dramcore)
             self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
 
-            # map the DRAM onto Wishbone
-            drambone = gramWishbone(dramcore)
+            # map the DRAM onto Wishbone, XXX use stall but set classic below
+            drambone = gramWishbone(dramcore, features={'stall'})
             if fpga == 'sim':
                 self.drambone = drambone
             else:
@@ -418,7 +418,10 @@ class DDR3SoC(SoC, Elaboratable):
         if hasattr(self, "ddrphy"):
             m.submodules.ddrphy = self.ddrphy
             m.submodules.dramcore = self.dramcore
-            m.submodules.drambone = self.drambone
+            m.submodules.drambone = drambone = self.drambone
+            # grrr, same problem with drambone: not WB4-pipe compliant
+            comb += drambone.bus.stall.eq(drambone.bus.cyc & ~drambone.bus.ack)
+
         # add blinky lights so we know FPGA is alive
         if platform is not None:
             m.submodules.blinky = Blinky()

diff --git a/src/simsoctb.v b/src/simsoctb.v
index 3ba4c910b50f012984f6b549f39de6acd58065b0..64fb39a1bf02f772acb8846c487cba04a4e78d16 100644 (file)
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -47,7 +47,7 @@ module simsoctb;
   ddr3 #(
     .check_strict_timing(0)
   ) ram_chip (
-    .rst_n(~dram_rst),
+    .rst_n(dram_rst),
     .ck(dram_ck),
     .ck_n(~dram_ck),
     .cke(dram_cke),