self.alu = pkls(self.in_pspec, self.out_pspec, modkls)
ReservationStations.__init__(self, num_rows)
- def i_specfn(self):
- return FPBaseData(self.in_pspec)
-
- def o_specfn(self):
- return FPPackData(self.out_pspec)
-
class FPClassMuxInOut(FPClassMuxInOutBase):
""" Reservation-Station version of FPClass pipeline.
""" Reservation-Station version of FPCVT pipeline.
* fan-in on inputs (an array of FPBaseData: a,b,mid)
- * 2-stage multiplier pipeline
+ * converter pipeline (alu)
* fan-out on outputs (an array of FPPackData: z,mid)
Fan-in and Fan-out are combinatorial.
self.alu = pkls(modkls, e_extra, self.in_pspec, self.out_pspec)
ReservationStations.__init__(self, num_rows)
- def i_specfn(self):
- return FPBaseData(self.in_pspec)
-
- def o_specfn(self):
- return FPPackData(self.out_pspec)
-
class FPCVTF2IntMuxInOut(FPCVTMuxInOutBase):
""" Reservation-Station version of FPCVT pipeline.
self.pspec = PipelineSpec(width, self.id_wid, op_wid)
self.alu = FPADDBasePipe(self.pspec)
ReservationStations.__init__(self, num_rows)
-
- def i_specfn(self):
- return FPBaseData(self.pspec)
-
- def o_specfn(self):
- return FPPackData(self.pspec)
# self.alu = FPDIVBasePipe(new_pspec)
self.alu = FPDIVBasePipe(self.pspec)
ReservationStations.__init__(self, num_rows)
-
- def i_specfn(self):
- return FPBaseData(self.pspec)
-
- def o_specfn(self):
- return FPPackData(self.pspec)
-"""IEEE Floating Point Multiplier Pipeline
+"""IEEE754 Floating Point Multiplier Pipeline
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jake Lifshay
Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=77
self.pspec = PipelineSpec(width, self.id_wid, self.op_wid)
self.alu = FPMULBasePipe(self.pspec)
ReservationStations.__init__(self, num_rows)
-
- def i_specfn(self):
- return FPBaseData(self.pspec)
-
- def o_specfn(self):
- return FPPackData(self.pspec)
-# IEEE Floating Point Multiplier
+"""IEEE754 Floating Point Multiplier
+
+Copyright (C) 2019 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Copyright (C) 2019 Jake Lifshay
+
+"""
from nmigen import Module, Signal, Cat, Const
from nmigen.cli import main, verilog
* data goes through a pipeline
* results fan back out.
- the output data format has to have a member "mid", which is used
+ the output data format has to have a member "muxid", which is used
as the array index on fan-out
"""
Input: num_rows - number of input and output Reservation Stations
- Requires: the addition of an "alu" object, an i_specfn and an o_specfn
+ Requires: the addition of an "alu" object, from which ispec and ospec
+ are taken, and inpipe and outpipe are connected to it
* fan-in on inputs (an array of FPADDBaseData: a,b,mid)
* ALU pipeline
def ports(self):
return self._ports
+ def i_specfn(self):
+ return self.alu.ispec()
+ def o_specfn(self):
+ return self.alu.ospec()
if stage is not None:
self.set_specs(self, self)
- def ospec(self, name):
+ def ospec(self, name=None):
assert self._ospecfn is not None
return _spec(self._ospecfn, name)
- def ispec(self, name):
+ def ispec(self, name=None):
assert self._ispecfn is not None
return _spec(self._ispecfn, name)