src/soc/fu/ldst/loadstore.py: add skeleton for fsm

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 0397f87d1488c812b0b40bca31132873d2fd920b..bec6536da39bd3f1118462ffa4f7e78cc19dce55 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -99,6 +99,26 @@ class LoadStore1(PortInterfaceBase):
         #self.nia           = Signal(64)
         #self.srr1          = Signal(16)
 
+        # fsm skeleton
+        with m.Switch(self.state):
+            with m.Case(State.IDLE):
+                pass
+            with m.Case(State.SECOND_REQ):
+                # req.eq(1);
+                # v.state.eq(ACK_WAIT)
+                # v.last_dword.eq(0);
+                pass
+            with m.Case(State.ACK_WAIT):
+                pass
+            with m.Case(State.MMU_LOOKUP):
+                pass
+            with m.Case(State.TLBIE_WAIT):
+                pass
+            with m.Case(State.FINISH_LFS):
+                pass
+            with m.Case(State.COMPLETE):
+                pass
+
     def set_wr_addr(self, m, addr, mask, misalign):
         m.d.comb += self.load.eq(0) # store operation