initialise XER from simulation

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 5ba3b91727bb357e1c87a762ebde1a2df6ffc8b0..ba732bedd81c3dba21dbecb19fa03813ff15859b 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -102,7 +102,7 @@ class XERRegs(VirtualRegPort):
     CA=1 # CA and CA32
     OV=2 # OV and OV32
     def __init__(self):
-        super().__init__(6, 2)
+        super().__init__(6, 3)
         self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
                         self.write_port("dest1"),
                         self.write_port("dest2"),

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 1e95f433f9e09be2c924679ed8fc4a4ba1008087..68357ac2a0a9e5a321ae6ef4c225fb9ac6893ced 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -1,12 +1,13 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, Cat
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
+from soc.decoder.isa.caller import special_sprs
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_decoder2 import PowerDecode2
 from soc.decoder.isa.all import ISA
-from soc.decoder.power_enums import Function
+from soc.decoder.power_enums import Function, XER_bits
 
 
 from soc.simple.core import NonProductionCore
@@ -149,6 +150,24 @@ class TestRunner(FHDLTestCase):
                 for i in range(32):
                     yield core.regs.int.regs[i].reg.eq(test.regs[i])
 
+                # set up XER
+                xregs = core.regs.xer
+                print ("sprs", test.sprs)
+                if special_sprs['XER'] in test.sprs:
+                    xer = test.sprs[special_sprs['XER']]
+                    sobit = xer[XER_bits['SO']].asint()
+                    yield xregs.regs[xregs.SO].reg.eq(sobit)
+                    cabit = xer[XER_bits['CA']].asint()
+                    ca32bit = xer[XER_bits['CA32']].asint()
+                    yield xregs.regs[xregs.CA].reg.eq(Cat(cabit, ca32bit))
+                    ovbit = xer[XER_bits['OV']].asint()
+                    ov32bit = xer[XER_bits['OV32']].asint()
+                    yield xregs.regs[xregs.OV].reg.eq(Cat(ovbit, ov32bit))
+                else:
+                    yield xregs.regs[xregs.SO].reg.eq(0)
+                    yield xregs.regs[xregs.OV].reg.eq(0)
+                    yield xregs.regs[xregs.CA].reg.eq(0)
+
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]