arch-power: Add PC-relative arithmetic instructions

This adds the following instructions.
  * Add PC Immediate Shifted (addpcis)

Change-Id: Ib88b8e123ffb328e6f692e0fddb237e420ce38a7
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index 015ed723dda2165166da34b79f688077acf280d7..d2862ff39126ae533b767d8a36637ae799a03a52 100644 (file)
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -223,6 +223,58 @@ IntImmArithOp::generateDisassembly(
 }
 
 
+std::string
+IntDispArithOp::generateDisassembly(
+        Addr pc, const Loader::SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    bool printSrcs = true;
+    bool printDisp = true;
+    bool negateDisp = false;
+
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("addpcis")) {
+        printSrcs = false;
+        if (disp == 0) {
+            myMnemonic = "lnia";
+            printDisp = false;
+        } else if (disp < 0) {
+            myMnemonic = "subpcis";
+            negateDisp = true;
+        }
+    }
+
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, destRegIdx(0));
+    }
+
+    // Print the source register
+    if (_numSrcRegs > 0 && printSrcs) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, srcRegIdx(0));
+    }
+
+    // Print the displacement
+    if (printDisp) {
+        if (negateDisp) {
+            ss << ", " << -disp;
+        } else {
+            ss << ", " << disp;
+        }
+    }
+
+    return ss.str();
+}
+
+
 std::string
 IntShiftOp::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const

diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 32c1ccd37ccec8a076d569d1b7658bd02f40e76e..a75f38b0cc1eb831fe18c0c1dd1cc7302ed558fc 100644 (file)
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -180,6 +180,27 @@ class IntImmArithOp : public IntArithOp
 };
 
 
+/**
+ * Class for integer arithmetic operations with displacement.
+ */
+class IntDispArithOp : public IntArithOp
+{
+  protected:
+
+    int32_t disp;
+
+    /// Constructor
+    IntDispArithOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+      : IntArithOp(mnem, _machInst, __opClass),
+        disp((int16_t)((machInst.d0 << 6) | (machInst.d1 << 1) | machInst.d2))
+    {
+    }
+
+    std::string generateDisassembly(
+            Addr pc, const Loader::SymbolTable *symtab) const override;
+};
+
+
 /**
  * Class for integer operations with a shift.
  */

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e678f0e7a374299f09fb643ddf3486d38a679d17..ff4fecea9a96542b4b9de265b3a81df11483ae9c 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -120,6 +120,12 @@ decode PO default Unknown::unknown() {
         format MiscOp {
             150: isync({{ }}, [ IsSerializeAfter ]);
         }
+
+        default: decode DX_XO {
+            format IntDispArithOp {
+                2: addpcis({{ Rt = NIA + (disp << 16); }});
+            }
+        }
     }
 
     17: IntOp::sc({{ return std::make_shared<SESyscallFault>(); }});

diff --git a/src/arch/power/isa/formats/integer.isa b/src/arch/power/isa/formats/integer.isa
index aa9cc2539b302a3986b930ca065cc5c662e5f025..cb858a8e356bcc9c5654102b1ba58bc966e69fe5 100644 (file)
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -206,6 +206,17 @@ def format IntImmLogicOp(code, computeCR0 = 0, inst_flags = []) {{
 }};
 
 
+// Integer instructions with displacement that perform arithmetic.
+// There are no control flags to set.
+def format IntDispArithOp(code, inst_flags = []) {{
+
+    # Generate the class
+    (header_output, decoder_output, decode_block, exec_output) = \
+        GenAluOp(name, Name, 'IntDispArithOp', code, inst_flags, BasicDecode,
+                 BasicConstructor)
+}};
+
+
 // Integer instructions that perform logic operations. The result is
 // always written into Ra. All instructions have 2 versions depending on
 // whether the Rc bit is set to compute the CR0 code. This is determined