make global pending sync-delayed

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 3c97c19af99c9938c86a056477492864244ca948..2edf65875541588562bb6efcdf9bcdc9ce4ffa8b 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -54,7 +54,7 @@ class ComputationUnitNoDelay(Elaboratable):
         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 
         with m.If(self.go_rd_i):
-            m.d.sync += self.counter.eq(2)
+            m.d.sync += self.counter.eq(1)
         with m.If(self.counter > 0):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 707a0ea35bb7c59059533e790ab9150b9ea2b59c..b0318b901befa993c191a6f0392fd81f107f04f0 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -104,8 +104,8 @@ class Scoreboard(Elaboratable):
         # NOTE: number of vectors is NOT same as number of FUs.
         g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
         g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
-        g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
-        g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
+        g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v, True)
+        g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v, True)
         m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
         m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
         m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
@@ -168,8 +168,8 @@ class Scoreboard(Elaboratable):
 
         # Connect INT Fn Unit global wr/rd pending
         for fu in if_l:
-            m.d.sync += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
-            m.d.sync += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
+            m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
+            m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 
         # Connect Picker
         #---------
@@ -183,7 +183,7 @@ class Scoreboard(Elaboratable):
         #---------
         # Connect Register File(s)
         #---------
-        m.d.sync += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
+        m.d.comb += int_dest.wen.eq(g_int_wr_pend_v.g_pend_o)
         m.d.comb += int_src1.ren.eq(g_int_src1_pend_v.g_pend_o)
         m.d.comb += int_src2.ren.eq(g_int_src2_pend_v.g_pend_o)
 
@@ -318,9 +318,9 @@ def scoreboard_sim(dut, alusim):
             src2 = 6
             dest = 1
         else:
-            src1 = 1
+            src1 = 3
             src2 = 7
-            dest = 1
+            dest = 2
         #src1 = 2
         #src2 = 3
         #dest = 2 
@@ -337,7 +337,6 @@ def scoreboard_sim(dut, alusim):
         yield
         yield
         yield
-        yield
         while True:
             issue_o = yield dut.issue_o
             if issue_o: