get jtag tests running on basic adder

diff --git a/ls180/post_pnr/cocotb/run_ghdl.sh b/ls180/post_pnr/cocotb/run_ghdl.sh
index 6c5e05b5577e3b8189a90b08c500b7faedba52f6..bff78daabd06d80539691cfc06d51058267c5f4a 100755 (executable)
--- a/ls180/post_pnr/cocotb/run_ghdl.sh
+++ b/ls180/post_pnr/cocotb/run_ghdl.sh
@@ -5,7 +5,7 @@ make \
   SIM=ghdl \
   COCOTB_RESULTS_FILE=results_iverilog.xml \
   COCOTB_HDL_TIMEUNIT=100ps \
-  TESTCASE="idcode_reset,idcodesvf_reset" \
+  TESTCASE="idcode_reset,idcodesvf_reset,idcode_run,idcode_run_svf" \
   SIM_BUILD=sim_build_iverilog
 
 

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index cc118d57de4fb6a7e7223bec4f28f248011c4828..4d79d0b2047a9061edd3f3f12c7385c00b4fbaa9 100644 (file)
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -7,6 +7,21 @@ from cocotb.binary import BinaryValue
 from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
 from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
 
+from itertools import chain
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Timer
+from cocotb.utils import get_sim_steps
+from cocotb.binary import BinaryValue
+
+from c4m.nmigen.jtag.tap import IOType
+from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
+from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
+
+from soc.config.pinouts import get_pinspecs
+from soc.debug.jtag import Pins
+
 #
 # Helper functions
 #
@@ -23,6 +38,10 @@ def setup_sim(dut, *, clk_period, run):
     dut.iovss <= 0
     dut.sys_rst <= 1
     dut.sys_clk <= 0
+    # adder test (ignore)
+    #dut.a <= 3
+    #dut.b <= 2
+
     if run:
         yield Timer(int(10.5*clk_steps))
         dut.sys_rst <= 0
@@ -32,9 +51,10 @@ def setup_jtag(dut, *, tck_period):
     # Make this a generator
     if False:
         yield Timer(0)
+    clk_steps = get_sim_steps(tck_period, "ns")
     return JTAG_Master(dut.jtag_tck, dut.jtag_tms,
                        dut.jtag_tdi, dut.jtag_tdo,
-                       clk_period=tck_period,
+                       clk_period=clk_steps,
                        ir_width=4)
 
 def execute_svf(dut, *, jtag, svf_filename):
@@ -107,7 +127,7 @@ def idcodesvf_reset(dut):
     dut._log.info("IDCODE test completed")
 
 @cocotb.test()
-def idcode_run(dut):
+def idcode_run_svf(dut):
     dut._log.info("Running IDCODE through test; cpu running...")
 
     clk_period = 100 # 10MHz
@@ -120,21 +140,6 @@ def idcode_run(dut):
 
     dut._log.info("IDCODE test completed")
 
-from itertools import chain
-
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import Timer
-from cocotb.utils import get_sim_steps
-from cocotb.binary import BinaryValue
-
-from c4m.nmigen.jtag.tap import IOType
-from c4m.cocotb.jtag.c4m_jtag import JTAG_Master
-from c4m.cocotb.jtag.c4m_jtag_svfcocotb import SVF_Executor
-
-from soc.config.pinouts import get_pinspecs
-from soc.debug.jtag import Pins
-
 
 @cocotb.test()
 def wishbone_basic(dut):