update comments

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index 2096a66783e43b43010a4f3c8e85714fa654fb4b..46d9629ca9a1148e8ed61a0f59e28c69a8faa762 100644 (file)
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -1,5 +1,15 @@
 """IEEE754 Floating Point pipelined Divider
 
+This module simply constructs register-based pipeline(s) out of
+appropriate combinatorial blocks: setup, intermediary and final
+single-clock pipelines.
+
+"actual" processing is carried out by the DivPipeCalculateStage
+combinatorial block: everything else is chaining and pre- and post-
+data formatting.
+
+there's no "actual" work done here: it's just a "joining-together" job.
+
 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
 
 """