Enable DDR3 using a 50MHz clock on Versa 85

diff --git a/src/ls2.py b/src/ls2.py
index 54251e3539800c9e69898aedcd9ddc99c80186f4..9deacd4781beb52593ebcf023008c90b43bb41c4 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -642,11 +642,11 @@ def build_platform(fpga, firmware):
     if fpga == 'sim':
         clk_freq = 100e6
     if fpga == 'isim':
-        clk_freq = 50e6 # below 50 mhz, stops DRAM being enabled
+        clk_freq = 55e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
         clk_freq = 50e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
-        clk_freq = 55e6
+        clk_freq = 50e6 # 50MHz works.  100MHz works.  55MHz does NOT work.  Stick with multiples of 50MHz...
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
@@ -667,11 +667,11 @@ def build_platform(fpga, firmware):
 
     # get DDR resource pins, disable if clock frequency is below 50 mhz for now
     ddr_pins = None
-    if (clk_freq > 50e6 and platform is not None and
+    if (clk_freq >= 50e6 and platform is not None and
         fpga in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']):
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
-                                    xdr={"rst": 4, "clk":4, "a":4,
+                                    xdr={"rst": 1, "clk":4, "a":4,
                                          "ba":4, "clk_en":4,
                                          "odt":4, "ras":4, "cas":4, "we":4,
                                          "cs": 4})