resolving issues with div tests (turned out to be nmutil.divmod)

adding more tests to track down a CR0 issue

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index fb6a4025346affe97ddeea2bfbafdbd11647d72c..2fe7ac085ba7b9ffe77f2501b9c14492222d866d 100644 (file)
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -75,6 +75,30 @@ class DIVTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
+    def test_0_regression(self):
+        for i in range(40):
+            lst = ["divwo 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = 0xbc716835f32ac00c
+            initial_regs[2] = 0xcdf69a7f7042db66
+            self.run_tst_program(Program(lst), initial_regs)
+
+    def test_0_regression(self):
+        for i in range(40):
+            lst = ["divwo 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = 0x10000000000000000-4
+            initial_regs[2] = 0x10000000000000000-2
+            self.run_tst_program(Program(lst), initial_regs)
+
+    def test_0_regression(self):
+        for i in range(40):
+            lst = ["divwo 3, 1, 2"]
+            initial_regs = [0] * 32
+            initial_regs[1] = 0xffffffffffff9321
+            initial_regs[2] = 0xffffffffffff7012
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_rand_divw(self):
         insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 610f7f86086faf88678d33d3a89029619ccc6879..a6f186016505f5ed13cf41cae33dfdc192f40944 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -32,6 +32,22 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_1_divw_(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "divw.  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def test_2_divw_(self):
+        lst = ["addi 1, 0, 0x1234",
+               "addi 2, 0, 0x5678",
+               "divw.  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def test_1_divwe(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -56,6 +72,16 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
+    def test_5_div_regression(self):
+        lst = ["addi 1, 0, 0x4",
+               "addi 2, 0, 0x2",
+               "neg 2, 2",
+               "neg 1, 1",
+               "divwo  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):
         initial_regs = [0] * 32